Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2008-09-09
2008-09-09
Jeanglaude, Jean B (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S144000, C341S172000, C341S143000
Reexamination Certificate
active
11616468
ABSTRACT:
A digital to analog converter (DAC) includes a first continuous-time stage that receives an input signal associated with a digital signal and performs continuous-time digital-to-analog conversion operations on the input signal. The first continuous-time stage outputs a first output signal. A second switched-capacitor stage receives the first output signal and performs switched-capacitor filtering of the first output signal. The second switched-capacitor stage outputs a second output signal that is sent to a low pass filter to form a continuous analog signal associated with the digital signal.
REFERENCES:
patent: 5072219 (1991-12-01), Boutaud et al.
patent: 5245344 (1993-09-01), Sooch
patent: 5451950 (1995-09-01), Vincelette et al.
patent: 5920273 (1999-07-01), Hirano
patent: 6118399 (2000-09-01), Krone
patent: 6522277 (2003-02-01), Fujimori et al.
patent: 6803869 (2004-10-01), Melanson et al.
patent: 6861968 (2005-03-01), Melanson et al.
patent: 2005/0073453 (2005-04-01), Cheng et al.
Adams et al., “A 113-dB SNR Oversampling DAC with Segmented Noise-Shpaed Scrambling” IEEE Journal of solid-State Circuits, vol. 33, No. 12, Dec. 1998, pp. 1871-1878.
Quiting et al., “Use of Oversampled Modulator for Analogue Adaptive FIR Filters Based on LMS Algorithm” Electronics Letters, XP-002437462, Apr. 9, 1992, vol. 28, No. 8, pp. 751-753.
Su et al., “A CMOS Oversampling D/A Converter with a Current-Mode Semidigital Reconstruction Filter” 8107 IEEE Journal of Solid-State Circuits, Dec. 28, 1993, No. 12, New York, pp. 1224-1233.
Adams Robert
Baginski Paul A.
Nguyen Khiem
Analog Devices Inc.
Gauthier & Connors LLP
Jeanglaude Jean B
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