Architecture and related methods for efficiently performing...

Details Architecture and related methods for efficiently performing... Architecture and related methods for efficiently performing...

2008-09-09

2008-09-09

Ngo, Chuong D (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S622000

Reexamination Certificate

active

09823928

ABSTRACT:
A method is presented comprising analyzing two or more input terms on a per-bit basis within each level of bit-significance. Maximally segmenting each of the levels of bit-significance into one or more one-, two-, and/or three-bit groups, and designing a hyperpipelined hybrid Wallace tree adder utilizing one or more full-adders, half-adders, and associated register based, at least in part, on the maximal segmentation of the input terms.

REFERENCES:
patent: 4706211 (1987-11-01), Yamazaki et al.
patent: 5724276 (1998-03-01), Rose et al.
patent: 5754459 (1998-05-01), Telikepalli
patent: 5935201 (1999-08-01), Costa et al.
patent: 6427156 (2002-07-01), Chapman et al.
patent: 6535901 (2003-03-01), Grisamore

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