Architecture and methods for a hardware description language sou

Details Architecture and methods for a hardware description language sou Architecture and methods for a hardware description language sou

1994-06-03

2000-10-17

Hafiz, Tariq R.

Boots, shoes, and leggings

364489, G06F 9445, G06F 945, G06F 1500

Patent

active

061321095

ABSTRACT:
This invention provides a method for displaying circuit analysis results corresponding to parts of the circuit near the portion of the hardware description language (HDL) specification that generated that part of the circuit. The invention also includes a method for using probe statements in the HDL specification to mark additional points in the initial circuit that should not be eliminated during optimization. This improves the ability to display circuit analysis results near the appropriate part of the HDL specification.

REFERENCES:
patent: 4546435 (1985-10-01), Herbert et al.
patent: 4667290 (1987-05-01), Goss et al.
patent: 4703435 (1987-10-01), Darringer et al.
patent: 4827427 (1989-05-01), Hyduke
patent: 4852173 (1989-07-01), Bahl et al.
patent: 4866663 (1989-09-01), Griffin
patent: 4868770 (1989-09-01), Smith et al.
patent: 4882690 (1989-11-01), Shinsha et al.
patent: 4907180 (1990-03-01), Smith
patent: 4942536 (1990-07-01), Watanabe et al.
patent: 4942615 (1990-07-01), Hirose
patent: 4967386 (1990-10-01), Maeda et al.
patent: 4970664 (1990-11-01), Kaiser et al.
patent: 5111413 (1992-05-01), Lazensky et al.
patent: 5146583 (1992-09-01), Matsunaka et al.
patent: 5191541 (1993-03-01), Landman et al.
patent: 5191646 (1993-03-01), Naito et al.
patent: 5265254 (1993-11-01), Blasciak et al.
patent: 5282146 (1994-01-01), Aihara et al.
patent: 5282148 (1994-01-01), Poirot et al.
patent: 5329471 (1994-07-01), Swoboda et al.
patent: 5335191 (1994-08-01), Kundert et al.
patent: 5377997 (1995-01-01), Wilden et al.
patent: 5437037 (1995-07-01), Furuichi
patent: 5446900 (1995-08-01), Kimelman
patent: 5452239 (1995-09-01), Dai et al.
patent: 5493507 (1996-02-01), Shinde et al.
patent: 5530841 (1996-06-01), Gregory et al.
patent: 5541849 (1996-07-01), Rostoker et al.
patent: 5544066 (1996-08-01), Rostoker et al.
patent: 5544067 (1996-08-01), Rostoker et al.
patent: 5544068 (1996-08-01), Takimoto et al.
patent: 5553002 (1996-09-01), Dangelo et al.
patent: 5555201 (1996-09-01), Dangelo et al.
patent: 5557531 (1996-09-01), Rostoker et al.
patent: 5581738 (1996-12-01), Dambrowski
Weiss, Ray, "ASIC's forcing logic synthesis' hand," Electronic Engineering Times, n516, T16 (pp. 1-2), Dec. 12, 1988.
Weiss, Ray, "Designers moving toward high-level logic representation via logic synthesis--Logic synthesis edging up design hierarchy," Electronic Engineering Times, n526, 81, (pp. 1-10), Feb. 6, 1989.
Weiss, Ray, "Synopsys fine-tunes logic synthesis," Electronic Engineering Times, n534, 138 (pp. 1-3), Apr. 17, 1989.
Brian Ebert et al., "SeeSaw: A Verilog Synthesis Viewer," 2nd Annual International Verilog HDL Conference, Design Excellence for Today and Tomorrow; Santa Clara, CA, Mar. 22-24, 1993, pp. 55-60.
Lis et al., "VHDL Synthesis Using Structured Modeling," 26th ACM/IEEE Design Automation Conference, Jun. 25, 1989, pp. 606-609.
Sougata Mukherjea, et al., "Applying Algorithm Animation Techniques for Program Tracing, Debugging, and Understanding," Proceedings 15th International Conference on Software Engineering, May 17, 1993, Baltimore, MD, pp. 456-465.
Design Analyzer Reference (per paper #9), "Text Viewer," v.3.1, pp. 1-15, Mar. 1994.
D. E. Thomas et al., "Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench," pp. 257-274, publication date unknown.
Pure Software Inc., Pure Coverage Data Sheet (Web Page), copyright 1996.
Pure Software Inc., Quantify Data Sheet (Web Page), copyright 1996.
Pure Software Inc., Purify, Finding Run-Time Memory Errors (Web Page), coyright 1996.
Reed Hastings et al., Pure Software, Inc., Purify, Usenix White Paper on Purify (Web Page), copyright 1996.
Printout of Web Page for Centerline, Code Center, Release 4, Nov. 1994.
HDC Computer Corporation, FirstApps User's Guide, pp. 112-116, copyright 1992.
Louis Trevillyan, "An Overview of Logic Synthesis Systems," 1987, pp. 166-172.
Timothy Kam, "Comparing Layouts with HDL Models: A Formal Verification Technique," 1992, pp. 588-591.
"A Programming the User Interface", Manual of Symbolics, Inc., 4 New England Tech Center, 555 Virginia Road, Concord, MA 01742, title page, pp. iii-v and pp. 1-134, Sep. 1986.

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