Architecture and method for testing VLSI processors

Details Architecture and method for testing VLSI processors Architecture and method for testing VLSI processors

1983-11-14

1986-06-24

Atkinson, Charles E.

Excavating

324 73R, G01R 3128

Patent

active

045970807

ABSTRACT:
A method and apparatus for testing VLSI processors using a bit-sliced bus-oriented data path include data and control monitors and BIT for the on-chip memory. The data monitor is used to compress output data produced by the data path. BIT implementation of a functional test coupled with the data monitor are used for an off-line self-test of the data path in field. The control monitor is used to decouple the testing task of the control section from that of the data path.

REFERENCES:
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patent: 4498172 (1985-02-01), Bhavsar
patent: 4503536 (1985-03-01), Panzar
patent: 4503537 (1985-03-01), McAnney
Konemann et al., Built-in Test for Complex Digital Integrated Circuits, Fifth European Solid State Circuits Conf., ESSCIRC 79, Southampton, England, Sep. 18-21, 1979, pp. 89-90.
Fasang, Circuit Module Implements Practical Self-Testing, Electronics, vol. 88, No. 1557, May 19, 1982, pp. 164-167.
Hahn et al., VLSI Testing by On-Chip Error Detection, IBM Tech. Disclosure Bulletin, vol. 25, No. 2, Jul. 1982, p. 709.
Carter, Improved Signature Test for VLSI Circuits, IBM Tech. Disclosure Bulletin, vol. 26, No. 3A, Aug. 1983 pp. 965-967.

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