Image analysis – Image compression or coding – Parallel coding architecture
Reexamination Certificate
2003-12-19
2008-11-11
Bella, Matthew C (Department: 2624)
Image analysis
Image compression or coding
Parallel coding architecture
C375S240190
Reexamination Certificate
active
07450770
ABSTRACT:
The present invention provides a high-speed, memory efficient parallel coding technique for embedded block coding with optimized truncation (EBCOT) used in still image compression. Attributing to parallel processing method and structure, it processes a discrete wavelet transform (DWT) coefficient at a clock cycle without any state variable stored. Therefore, the need of state variable memory can be avoid and the external memory bandwidth can be reduced. With the same cost of chip-area and lower power consumption, the processing rate of this invention is several times higher than conventional schemes. Furthermore, the present invention processes 50 M coefficients per second at 100 MHz and can encode lossless HDTV 720 p resolution pictures at 30 fps in real time.
REFERENCES:
patent: 6978048 (2005-12-01), Higginbottom et al.
Hung-Chi Fang, et al.; High Speed Memory Efficient Ebcot Architecture for JPEG2000; 2003; pp. II736-II739.
Hung-Chi Fang et al.; Novel Word-Level Algorithm of Embedded Block Coding in JPEG 2000; 2003; pp. I137-I140.
Chang Yu-Wei
Chen Liang-Gee
Fang Hung-Chi
Shih Ya-Yun
Wang Tu-Chih
Bella Matthew C
National Taiwan University
Perungavoor Sath V.
Troxell Law Office PLLC
LandOfFree
Architecture and method for parallel embedded block coding does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Architecture and method for parallel embedded block coding, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Architecture and method for parallel embedded block coding will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4027085