Architecture and device for testable mixed analog and digital VL

Details Architecture and device for testable mixed analog and digital VL Architecture and device for testable mixed analog and digital VL

1988-05-13

1990-05-01

Atkinson, Charles E.

Excavating

371 226, G01R 3128

Patent

active

049224921

ABSTRACT:
An architecture and device for testing mixed analog and digital VLSI circuits, wherein the digital circuit portions of the chip are grouped into a digital block, and the analog circuit protions of the chip are= grouped into an analog block. Analog signals are provided to the digital block through an A/D transducer, and digital signals are provided to the analog block through a D/A transducer. The analog and digital blocks may be isolated from each other by a digital input multiplexer disposed between the A/D transducer and the digital block, and by an analog input multiplexer disposed between the D/A transducer and the analog block. To minimize the number of pins required to implement the architecture, multiplexers are connected to accessed circuit nodes in the analog block and the digital block for selectively communicating signals from the accessed nodes to external output pins.

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H. Ando, "Testing VLSI With Random Access Scan," Compcon Spring Proceedings, 1980, pp. 243-245.

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