Architecture and circuits for eliminating skews in PLDs

Details Architecture and circuits for eliminating skews in PLDs Architecture and circuits for eliminating skews in PLDs

1993-11-15

1996-11-05

Bowler, Alyssa H.

Boots, shoes, and leggings

395500, 3642328, 3642715, 327262, G06F 1300

Patent

active

055727158

ABSTRACT:
A programmable logic device (PLD) architecture that minimizes the skew in the outputs of PLD devices in response to input signal transitions. The architecture emulates the worst case response condition of the memory array portion of the PLD and builds it into a dedicated emulation signal path, which is in parallel with the signal path of the real data between the input and output of the PLD. The output of the emulation signal path then controls the real data output path and thus the output of the PLD. The PLD output equals the real data path output only when the output of the emulation signal path is valid.

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