Arc detection architecture based on correlation for circuit...

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – For fault location

Reexamination Certificate

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Details

C324S536000

Reexamination Certificate

active

06242922

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to circuit breakers and, more particularly, to arc detection in residential type circuit breakers.
BACKGROUND OF THE INVENTION
Although detection of arcs is desirable to reduce the possibility of a fire being ignited by an arc and to protect building wiring and consumer wiring, such as extension cords and appliance cords, as well as appliances themselves, known residential type circuit breakers typically do not include an arc detection unit. Arcs can generally be identified by the high frequency content of current in a branch circuit. High frequency current, i.e., current having a frequency exceeding the range of 1 KHz to 10 MHz, can be introduced into the branch circuit through benign apparatus such as universal motors in hair driers, drills, and vacuum cleaners. Such motors can produce significant high frequency energy due to arcing of the brush motor commutation. Silicon controlled rectifier lamp dimmers and advanced electronic devices can also generate high frequency energy. Discriminating between actual arcing faults and benign sources of high frequency energy is therefore more difficult than merely sensing a high frequency. A residential arc detection unit, however, must have a low nuisance trip rate, i.e., low false alarm rate. Known arc detection units having the necessary low false alarm rate are complex and therefore expensive.
To reduce the costs of arc detection units, some known circuit breakers include central processing units that execute algorithms to eliminate possible noise sources, such as electric household appliances and tools (e.g., motors, welders, switches). Such known algorithms include fourier analysis and other frequency domain based approaches. The noise sources are eliminated from the primary signal by classifying the noise resulting from such sources, and then using such classified signals to identify noise signals and sources in the primary signal. The noise signals are then subtracted from the primary signal so that the noise portion of the signal is eliminated.
The functional requirements for digital signal processing based on elimination of noise sources requires correct classification of noise signals followed by storage of data, i.e., storage of the primary signal portion associated with the noise signal. The processing power necessary to provide this function is high and increases linearly with the number of noise sources present as well as about with the square of the frequency range considered due to the Fourier Transform requirements.
It would be desirable to provide protection for a residence from arc type faults, including fault isolation and location. It would also be desirable to provide such protection at a low cost as compared to the costs associated with using sophisticated arc detection units.
SUMMARY OF THE INVENTION
Apparatus for detecting arcs from a signal provided by a current sensor includes a mixed analog digital application specific integrated circuit (ASIC) employing a standard central processing unit (CPU) with a reduced digital signal processing (DSP) load and programmed to execute a correlation function for arc detection. Use of such a standard CPU is possible because the DSP overhead needed for digital fourier analysis is eliminated by the ASIC architecture. Further, by enabling use of a standard CPU, fabrication cost of the ASIC can be substantially less than the fabrication cost associated with known arc detection units.
In an exemplary embodiment, the ASIC includes a power supply configured to be coupled to an AC power line for supplying power to the ASIC components. The ASIC further includes a current sensor coupled to a current-carrying conductor of, for example, a circuit breaker. The current sensor is located adjacent the breaker current path so that the sensor generates a signal representative of current in the conductor. The ASIC further includes a first analog-to-digital converter (ADC) coupled in series with the current sensor. The first ADC has its output coupled to a central processing unit (CPU). The CPU may, for example, be a general purpose type CPU, which is well known in the art. Output signals of the first ADC can be used by the CPU to implement overcurrent-tripping algorithms, which also are well known in the art.
The CPU includes an output coupled to a digital-to-analog converter (DAC), and the CPU supplies the DAC with a digital signal representative of a portion of the sensed current. The DAC is coupled to a summer, which also is coupled to an output of the current sensor. The output of the summer is coupled to a second analog-to-digital converter (ADC), and the output signal of the second ADC is supplied as an input signal to the CPU. A CPU output is coupled to a trigger or actuator, e.g., a trigger of a circuit breaker.
In operation, the current sensor produces an analog signal representative of current in the circuit breaker conductor. The analog signal is converted to a digital signal by the first ADC, and the digital signal produced by the first ADC is supplied to the CPU. The CPU processes the received digital signal and filters the received digital signal to remove, for example, the noise portion of the digital signal. The filtering function can be achieved by standard digital signal processing techniques. The CPU then supplies to the DAC a substantially noise free digital signal, e.g., a substantially noise free 50 Hz or 60 Hz signal. The DAC converts the noise free digital signal to an analog signal, and the substantially noise free analog signal is supplied to the summer.
The summer subtracts the substantially noise free analog signal from the analog signal supplied by the current sensor so that the 50 Hz or 60 Hz signal component is removed therefrom. Subtracting the 50 Hz or 60 Hz signal component from the sensor output signal provides differential sensitivity improvement. The signal produced by the summer is then supplied to the second ADC which converts the summer output signal to a digital signal which is supplied to the CPU. The output signal of the second ADC substantially contains the noise generated by the arc with the 50 Hz or 60 Hz signal component removed for further processing at the higher sensitivity.
The CPU executes a correlation function using the digital signal received from the second ADC. One correlation function that can be used in the CPU is a sliding windows function that emulates fourier frequency analysis in real time, thus eliminating the need for digital fourier analysis and hence reducing the CPU processing power required and associated costs. Although the arc signature includes the frequency range of 1 KHz to 10 KHz, the detection can be limited to several hundreds of hertz, such as 300 Hz, up to several tens of KHz, such as 20 KHz, to best suit the processing speed available for simple CPUs. As higher processing speeds are made available at substantially the same cost with the advance of semiconductor circuitry, the range covered by the correlator can be extended. The exact choice between frequency range for the correlator and the number of correlation taps can be traded off with the detection accuracy. By limiting the frequency range to 300 Hz up to 20 Khz, contributions from parasitic noise sources, such as radio transmission, switching power supplies, and rectifiers are substantially eliminated while the arc energy in this frequency range is detected on a dominant basis. To further enhance the detection accuracy, a superimposed 50 Hz or 60 Hz half cycle signature may be used, thus distinguishing the arc from the signature of parasitic arcs, such as generated by motor brushes operating at different frequencies. The correlation algorithms employed by the invention are based on detection, not elimination of noise sources.
To perform the correlation type of function, one possibility is to provide for the computation of a set of band-pass type filters and perform them over multiples or fractional multiples of the fundamental frequency (i.e., 50 or 60 Hz). The filtered signals are then used to determi

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