Arbitration scheme for efficient parallel processing

Details Arbitration scheme for efficient parallel processing Arbitration scheme for efficient parallel processing

2005-11-08

2005-11-08

Bella, Matthew C. (Department: 2676)

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

C345S535000, C345S503000, C345S504000, C345S505000

Reexamination Certificate

active

06963342

ABSTRACT:
A system and method for assigning operations to multiple pipelines in a graphics system is disclosed. The graphics system may include an arbitration unit coupled to a plurality of calculation pipelines. The arbitration unit is operable to provide graphics operations to selected ones of the calculation pipelines. Each of the calculation pipelines is operable to perform a graphics operation. Each of the calculation pipelines may include digital logic and/or a processing element for performing the graphics operations. An operation may be assigned to a pipeline if the pipeline is performing a low latency operation. A low latency operation may comprise an operation that is performed by one of the calculation pipelines in less time than a pre-determined number of clock cycles.

REFERENCES:
patent: 5457779 (1995-10-01), Harrell
patent: 5907688 (1999-05-01), Hauck et al.
patent: 6567839 (2003-05-01), Borkenhagen et al.
patent: 6573905 (2003-06-01), MacInnis et al.
patent: 6624818 (2003-09-01), Mantor et al.

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