Multiplex communications – Channel assignment techniques – Using time slots
Reexamination Certificate
1999-10-01
2004-02-17
Hsu, Alpus H. (Department: 2733)
Multiplex communications
Channel assignment techniques
Using time slots
C370S447000, C370S428000
Reexamination Certificate
active
06693914
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an arbitration mechanism for packet transmission and is particularly but not exclusively concerned with packet transmission in an integrated circuit.
BACKGROUND TO THE INVENTION
Computer systems and integrated circuit processors exist which implement transactions with the dispatch and receipts of packets. Request packets define an operation to be performed and response packets indicate that a request has been received. The integrated circuit processor can comprise a plurality of functional modules connected to a packet router for transmitting and receiving the request and response packets. In such a system, it is necessary to arbitrate between requests received from the functional modules for controlling the flow of packets on the packet router (whether request or response packets) Typically, multiple functional modules are able to access the same bus or the same part of the system which leads to competition for that bus or for the same destination or target modules. The complexity of the arbitration mechanism is a function of the number of devices in the system and the arbitration algorithm which is used.
As the size and clock frequency of such systems, in particular integrated systems, increases, and the complexity of the arbitration function increases, the time required to make an arbitration decision for accesses to resources such as the system bus or target modules becomes critical. In many systems, it is not possible to make an arbitration decision and effect a packet transfer in a single clock cycle. This leads to a drop in potential performance as gaps are inserted increasing the latency between a request for packet transfer being made and the packet transfer actually being implemented.
It is an aim of the present invention to reduce the impact of arbitration decision latency on a system.
SUMMARY OF THE INVENTION
According to one aspect of the present invention there is provided a computer system comprising: a plurality of functional modules interconnected via a packet router, each functional module having packet handling circuitry for generating and receiving packets conveyed by the packet router; and a routing control mechanism for controlling the flow of packets on the packet router, said routing control mechanism being connected to said functional modules and to said packet router, wherein each functional module is operable to generate to the routing control mechanism a transfer request to request transfer of a current packet and an arbitration request with a destination indicator identifying a destination of a later packet and wherein the routing control mechanism is operable to accept said arbitration request with the destination indicator of the later packet and to effect a routing decision relating to the arbitration request while implementing the transfer of the current packet requested by the transfer request.
In the described embodiment, the arbitration request relates to a packet issued two cycles after the current packet by the same functional module. That is, the arbitration unit effectively hides a latency of two decision cycles. However, a latency period of at least one cycle still represents a considerable advantage. That is, transfer of a current packet can be implemented while a subsequent arbitration decision is effected. There can be any suitable number of cycles in the latency period.
At least a set of said functional modules can act as initiator modules for generating request packets for implementing transactions, each request packet including the destination indicator. A further set of the functional modules can act as target modules for receiving said request packets and for issuing respective response packets. The response packets can be arbitrated in the same way as request packets with associated response transfer and response arbitration request signals. Each functional module can be operable to generate a grant signal indicating that it is in a state to receive a packet. That grant signal is used by the routing control mechanism to effect packet transfers.
The routing control mechanism is preferably operable to issue an arbitration grant signal indicating that it has committed an arbitration decision to await transfer. This acts as a handshake mechanism to indicate to the functional modules that a arbitration request has been granted and the system is committed to transferring that packet. This allows the functional module to begin negotiation for an arbitration decision for a subsequent packet, possibly before the transfer of the previous packet.
In the preferred embodiment, each packet has an address field identifying a destination module using the destination indicator and identifying an address location within the target module to which the packet is to be directed. The arbitration request is associated with the destination indicator to allow arbitration decisions to be made while the transfer request is associated with the location within the target module.
Another aspect of the invention provides a functional module for connection to a packet router and having packet handling circuitry for generating and receiving packets conveyed by the packet router, the functional module being operable to generate packet flow control signals including a transfer request requesting transfer of a current packet and an arbitration request signal with a destination indicator identifying a destination of a later packet, wherein the arbitration request signal is issued when the later packet is ready for transfer.
Another aspect of the invention provides a routing control mechanism for routing packets between a plurality of functional modules interconnected via a packet router, the routing mechanism comprising: an arbitration mechanism for effecting routing decisions for each packet for which a request signal is received; a decision queue for holding at least one decision which has been made by the arbitration mechanism; and a transfer mechanism for transferring packets relating to queued decisions to the packet router to implement a packet transfer, wherein the arbitration mechanism is operable to effect a routing decision for a later packet while a current packet is being transferred by the transfer mechanism onto the packet router.
Another aspect of the invention provides a plurality of functional modules interconnected via a packet router, each functional module having packet handling circuitry for generating and receiving packets conveyed by the packet router; and a routing control mechanism for controlling the flow of packets on the packet router, said routing control mechanism being connected to said functional modules and to said packet router, the routing control mechanism comprising: an arbitration mechanism for effecting routing decisions for each packet for which a request signal is received; a queue for holding at least one routing decision which has been made by the arbitration mechanism; and a transfer mechanism for transferring packets relating to queued decisions to the packet router to implement a packet transfer, wherein the arbitration mechanism is operable to effect a routing decision for a later packet while a current packet is being transferred by the transfer mechanism onto the packet router.
Another aspect of the invention provides a method of effecting pipelined routing decisions in an integrated circuit comprising a plurality of functional modules interconnected via a packet router wherein each functional module generates a transfer request for a current packet and an arbitration request with a destination indicator of a later packet, the method comprising: effecting a transfer of the current packet based on an earlier routing control decision while making a routing control decision in relation to the later packet.
REFERENCES:
patent: 4814981 (1989-03-01), Rubinfeld
patent: 5251311 (1993-10-01), Kasai
patent: 5386565 (1995-01-01), Tanaka et al.
patent: 5402416 (1995-03-01), Cieslak et al.
patent: 5423050 (1995-06-01), Taylor et al.
patent: 5434804 (1995-07-01), Bock et
Carey John A.
Jones Andrew M.
Hsu Alpus H.
Jorgenson Lisa K.
Kubida William J.
STMicroelectronics Inc.
Tran Thien
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