Arbitration logic using a four-phase signaling protocol for cont

Details Arbitration logic using a four-phase signaling protocol for cont Arbitration logic using a four-phase signaling protocol for cont

1997-02-05

2000-05-16

Treat, William M.

Electrical computers and digital processing systems: processing

Architecture based instruction processing

Data flow based system

712 25, 712 33, G06F 1208, G06F 700

Patent

active

060651091

ABSTRACT:
A counterflow pipeline is provided which includes an instruction pipeline having a plurality of stages for transmitting instruction packets in a first direction and a result pipeline having a plurality of stages for transmitting result packets in a second direction opposite the first direction. Each of the result pipeline stages corresponds to an instruction pipeline stage, the associated instruction and result pipeline stages being part of a counterflow pipeline stage. Arbitration logic coupled between the instruction and result pipelines facilitates the movement of instruction and result packets in the stages of the instruction pipeline and result pipeline, respectively, using a four-phase level signaling protocol. The arbitration logic prevents instruction and result packets from passing each other in their respective pipelines by inhibiting them from being simultaneously released from adjacent counterflow pipeline stages. Thus, any necessary interaction between the two data packets may take place.

REFERENCES:
patent: 5544342 (1996-08-01), Dean
patent: 5572690 (1996-11-01), Molnar
patent: 5752070 (1998-05-01), Martin et al.
Sproull eta l. (Counter flow pipeline processor architecture) Sun Microsystems LAb, Inc. p. 1-23, Apr. 1994.

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