Patent
1993-06-09
1997-04-01
Harvey, Jack B.
395293, G06F 1318
Patent
active
056175450
ABSTRACT:
A parallel computer network wherein an arbitration circuit for performing arbitrating operation over a plurality of processing requests at the same time at high speed is provided in a crossbar network control circuit to thereby prevent the processing requests not selected from being kept awaited for a long time. The arbitration circuit includes a priority bit change circuit which has a plurality of adders for adding a preset value to the priority information of the each awaited processing request and also has a plurality of comparators for detecting the requests being awaited.
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patent: 4375639 (1983-03-01), Johnson, Jr.
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patent: 4814974 (1989-03-01), Narayanan et al.
patent: 5195185 (1993-03-01), Marenin
patent: 5317696 (1994-05-01), Hilgendorf
Hamanaka Naoki
Ogata Yasuhiro
Shutoh Shin'ichi
Takeuchi Shigeo
Toba Taturu
Harvey Jack B.
Hitachi , Ltd.
Hitachi VLSI Engineering Corporation
Seto Jeffrey K.
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