Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-05-10
2011-05-10
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S108000, C716S111000, C716S113000, C716S134000, C703S019000
Reexamination Certificate
active
07941775
ABSTRACT:
An approach for performing arbitrary waveform propagation through a logic gate using timing analysis results is described. In one embodiment, there is an arbitrary waveform propagation tool for determining an effect of noise on a digital integrated circuit having at least one logic gate. A timing analysis component is configured to perform a timing analysis on the at least one logic gate and a noise analysis component is configured to perform a noise analysis. A waveform propagation model synthesizer component is configured to dynamically synthesize a waveform propagation model as a function of the timing analysis. The waveform propagation model synthesizer component is further configured to apply an arbitrary voltage waveform comprising one of a noisy waveform or noise glitch waveform and determine an effect of the arbitrary voltage waveform on the at least one logic gate from the dynamically synthesized waveform propagation model.
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Abbaspour Soroush
Feldmann Peter
Dinh Paul
Hoffman Warnick LLC
International Business Machines - Corporation
Nguyen Nha T
Young Preston
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