Arbitral dynamic cache using processor storage

Details Arbitral dynamic cache using processor storage Arbitral dynamic cache using processor storage

1988-09-15

1990-08-07

Shaw, Gareth D.

Boots, shoes, and leggings

3642434, 36424341, 3649642, G06F 1200, G06F 1300

Patent

active

049473190

ABSTRACT:
A data cache in a computer operating system that dynamically adapts its size in response to competing demands for processor storage, and exploits the storage cooperatively with other operating system components. An arbiter is used to determine the appropriate size of the cache based upon competing demands for memory. The arbiter is entered cyclically and samples user's wait states. The arbiter then makes a decision to decrease or increase the size of the cache in accordance with predetermined parameters.

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patent: 4430712 (1984-02-01), Coulson et al.
patent: 4463424 (1984-07-01), Mattson et al.
patent: 4489378 (1984-12-01), Dixon et al.
patent: 4503501 (1985-03-01), Coulson et al.
patent: 4654782 (1987-03-01), Bannai et al.
Effects of Cache Coherency in Multiprocessors--Michel Dubois & Faye A. Briggs.

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