Arbiter circuits with metastable free outputs

Details Arbiter circuits with metastable free outputs Arbiter circuits with metastable free outputs

1988-03-14

1989-05-30

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307454, 307362, 328133, 3408255, H03K 1716, H03K 1730

Patent

active

048354228

ABSTRACT:
A high-speed low-power-consumption two-input arbiter circuit comprises two input inverters, two inverters cross-coupled to form a latch and two additional inverters that drive a difference detector. The detector responds only to a voltage difference on its inputs that exceeds a specified value. In this way, signals are blocked from appearing at the outputs of the detector while the latch is in a metastable state. Additionally, an n-input arbiter circuit comprises (n-1)+(n-2)+ . . . +[n-(n-1)] two-input arbiter circuits and logic circuitry connected to the outputs of the two-input circuits for supplying a priority signal to one and only one at a time of n output terminals of the n-input circuit.

REFERENCES:
patent: 3311881 (1967-03-01), Mellott
patent: 4034303 (1977-07-01), Kodaira
patent: 4225795 (1980-09-01), Keeney
patent: 4398101 (1983-08-01), Friauf
patent: 4403192 (1983-09-01), Williman
patent: 4423384 (1983-12-01), DeBock
patent: 4475049 (1984-10-01), Smith et al.
patent: 4502014 (1985-02-01), Bismarck
patent: 4620118 (1986-10-01), Barber
patent: 4663620 (1987-05-01), Paul et al.
"Differential Latched Receiver Circuit", IBM T.D.B., vol. 29, No. 3, Aug. 1986, p. 1414.

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