Arbiter circuit using plural-reset RS flip-flops

Details Arbiter circuit using plural-reset RS flip-flops Arbiter circuit using plural-reset RS flip-flops

1990-06-14

1991-11-12

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 364200, 36518904, H03K 1716

Patent

active

050650521

ABSTRACT:
This invention is realized, in sum, by providing at least one reset input terminal, aside from a reset input terminal to which a request end signal is supplied, to output stage RS flip-flops of plural latch circuits to which plural request signals are supplied respectively. The signal of a first output terminal of the output stage RS flip-flop of a specified latch circuit of the plural latch circuits is supplied to a reset input terminal of the output stage RS flip-flop of the other latch circuit and a delay circuit is connected between a second output terminal and the other reset input terminal of the output stage RS flip-flops of each latch circuit. Accordingly, if plural request signals are supplied at substantially the same time, the competition of these request signals may be settled. Besides, by setting the delay time of each delay circuit longer than the time required from the supply of the signal to the set input terminal of the corresponding output stage RS flip-flop until the signal is latched in the output terminal, even if pulsive signals are supplied to the output stage RS flip-flops, oscillation of the output stage RS flip-flops may be prevented.

REFERENCES:
patent: 4314335 (1982-02-01), Pezzi
patent: 4398101 (1983-08-01), Friauf
patent: 4451881 (1984-05-01), Grice et al.
patent: 4757217 (1988-07-01), Sawada et al.
patent: 4864243 (1989-09-01), Reese
patent: 4918664 (1990-04-01), Platt
patent: 4967398 (1990-10-01), Jamoua et al.
patent: 4987559 (1991-01-01), Miyauchi et al.
patent: 4998027 (1991-03-01), Mihara et al.

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