Arbiter circuit for processing concurrent requests for access to

Communications: electrical – Continuously variable indicating – With meter reading

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3408255, 370 852, 307597, 307592, H04Q 120

Patent

active

049242202

ABSTRACT:
An arbiter circuit is disclosed for processing competing requests for access to a shared resource made simultaneously by two subsystems in a multi-processor system. The arbiter circuit includes an SR flip-flop composed of a pair of NAND gates, and functions to block the passage of a subsequent request signal from one subsystem to the SR flip-flop during a predetermined time interval after a request signal from the other subsystem has been supplied to the flip-flop. A result is that the both inputs of the SR flip-flop are not shifted up from the low levels to the high levels at the same time by the simultaneous generation of request signals from both subsystems, thereby eliminating any possibility of the output from the flip-flop floating at an intermediate level between the high and low level.

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T. Sakurai et al., "A 36ns 1Mbit Pseudo SRAM with VSRAM Mode" 1987 Symposium on VLSI Circuits, Digest of Technical Papers, IEEE Cat. No. 87 TH0190-9, May 22,23, 1987.

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