Arbiter circuit for processing concurrent requests for access to

Details Arbiter circuit for processing concurrent requests for access to Arbiter circuit for processing concurrent requests for access to

1988-11-18

1990-10-09

Yusko, Donald J.

Communications: electrical

Continuously variable indicating

With meter reading

370 852, 3408255, 3642426, 3642427, 36424292, H04Q 120

Patent

active

049623796

ABSTRACT:
An arbiter circuit is disclosed for processing requests made at least two subsystems in a multiprocessor system for access to a resource shared by the subsystems. The arbiter circuit includes an SR flip-flop composed of a pair of NAND gates. The flip-flop is operative in response to a time-staggered request signals from the subsystems to provide a request acknowledging signal to the shared resource. When two request signals are simultaneously supplied to the arbiter circuit, the outputs from the pair of NAND gates tend to stay at an intermediate level between the normal two distincitive logic levels, failing to produce an acknowledgment signal. However, the intermediate level of the NAND gate outputs is sensed by a NOR gate to a trigger a switching device into conduction, by means of which one of the intermediate NAND gate outputs is positively shifted to either of the active logic levels for the generation of an acknowledgement signal to the shared resources. Thus, one of the two subsystems is allowed access to the shared resource.

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T. Sakurai et al., "A 36ns 1Mbit Pseudo SRAM with VSRAM Mode" 1987 Symposium on VLSI Circuits, Digest of Technical Papers, IEEE Cat. No. 87, TH 0190-9, May 22,23, 1987.

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