Approximate state control mechanism

Details Approximate state control mechanism Approximate state control mechanism

2001-06-20

2004-11-23

Phunkulh, Bob A. (Department: 2661)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S429000

Reexamination Certificate

active

06822965

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to data handling systems and is more particularly concerned with the handling of data packets by peripheral controllers acting under the control of a central controller.
An example of such a system would be a data switching fabric (such as that described in International Patent Application PCT/GB99/03748), in which the peripheral controllers deal with the transmission and reception of packets of data, storing the packets in queues prior to their passage through the switching fabric. The central controller uses information about the size of the queues to influence how it creates connections within the switch fabric, generally aiming to keep the queue sizes as small as possible. In such a system, there could be a very large number of queues to keep track of, since there could be separate queues for each source/destination pair and also separate queues for different priority levels of packets. Keeping a copy of the exact size of each of these queues within the central controller might not be possible due to space limitations in the implementation of the central controller.
It is an object of the present invention to address the above issues.
EP 0624015A discloses an asynchronous transfer mode (ATM) switch having a plurality of input port servers connected to output port servers via a switch. The input port servers include buffers for cells. Whenever the number of cells in the queue reaches a threshold a request for bandwidth allocation is transmitted to the output port server. The output port server compares the requested bandwidth with the available bandwidth, and grants the bandwidth if sufficient bandwidth is available.
EP 0860960A discloses an ATM switch in which both input ports and output ports maintain buffers. A control unit is informed of the number of cells in the queues of the input buffers, and also receives information about the approximate number of cells in the output buffers.
The present invention proposes a data packet handling system having a plurality of peripheral controllers (PE
1
, PEN), each peripheral controller including at least one queue arranged to store packets of information received from a peripheral data packet source connected to that peripheral controller (PE
1
, PEN), each peripheral controller (PE
1
, PEN) having for each queue a corresponding detection means (PC) for performing a queue size detection logic to detect when the size of that queue traverses one of a plurality of queue size thresholds, and thereupon to transmit a corresponding threshold traversing signal;
characterized in that:
the system further includes a central controller (CC);
the detection means (PC) is arranged to transmit the threshold traversing signals to the central controller (CC); and
the central controller (CC) includes for each queue in each of the peripheral controllers (PE
1
, PEN) a corresponding queue size detection arrangement (CCASL) for detecting the size of the corresponding queue using the threshold traversing signals from the corresponding peripheral controller (PE
1
, PEN).
In the case of the data switching fabric described above, it is not actually necessary for the central controller to know the exact size of the queues in the peripheral controllers; an approximate scale along the lines of “Empty”, “Nearly Empty”, “Active”, “Busy”, “Very Busy”, “Nearly Full” and “Full” could be sufficient to base scheduling and arbitration decisions on. Representing this limited number of states in digital logic requires significantly less space in the central controller than representing the exact, precise size of the queues. The mapping between the exact and approximate queue sizes is performed in the peripheral controllers, each of which has a much smaller number of queues to manage and, therefore, the size of the logic required to hold the state and mapping information is less of an issue there.


REFERENCES:
patent: 5448559 (1995-09-01), Hayter et al.
patent: 5577035 (1996-11-01), Hayter et al.
patent: 5796719 (1998-08-01), Peris et al.
patent: 6307852 (2001-10-01), Fisher et al.
patent: 6490248 (2002-12-01), Shimojo
patent: 0624015 (1994-09-01), None
patent: 0860960 (1998-08-01), None
patent: 9714240 (1997-05-01), None

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