Approach to reduce parasitic capacitance from dummy fill

Details Approach to reduce parasitic capacitance from dummy fill Approach to reduce parasitic capacitance from dummy fill

2005-04-14

2008-12-30

Pizarro, Marcos D. (Department: 2891)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S735000, C438S633000, C257S758000, C257S752000, C257SE21581

Reexamination Certificate

active

07470630

ABSTRACT:
An integrated circuit includes a semiconductor substrate and multiple dielectric layers stacked on the substrate. Multiple interconnect metal lines and dummy metals are embedded in the dielectric layers. At least one of the dummy metals is substantially thinner than the interconnect metal lines. To form this structure, first and second pluralities of trenches are formed in the dielectric layer. At least one of the second plurality of trenches is shallower than the first plurality of trenches. The first and second pluralities of trenches are filled with a conductive layer and then planarized.

REFERENCES:
patent: 5459093 (1995-10-01), Kuroda et al.
patent: 5604156 (1997-02-01), Chung et al.
patent: 5741741 (1998-04-01), Tseng
patent: 6001733 (1999-12-01), Huang et al.
patent: 6184121 (2001-02-01), Buchwalter et al.
patent: 6319834 (2001-11-01), Erb et al.
patent: 6323117 (2001-11-01), Noguchi
patent: 6436807 (2002-08-01), Cwynar et al.
patent: 6492259 (2002-12-01), Dirahoui et al.
patent: 6627539 (2003-09-01), Zhao et al.
patent: 6717267 (2004-04-01), Kunikiyo
patent: 6961915 (2005-11-01), Loh et al.
patent: 7030022 (2006-04-01), Jung et al.
patent: 7071009 (2006-07-01), Wang et al.
patent: 7163870 (2007-01-01), Koubuchi et al.
patent: 7217649 (2007-05-01), Bailey et al.
patent: 2001/0027008 (2001-10-01), Matsumoto
patent: 2002/0110759 (2002-08-01), Lin et al.
patent: 2002/0167072 (2002-11-01), Andosca
patent: 2003/0027425 (2003-02-01), Kawanishi
patent: 2003/0151080 (2003-08-01), Hurley et al.
patent: 2004/0023499 (2004-02-01), Hellig et al.
patent: 2004/0029385 (2004-02-01), Manger et al.
patent: 2004/0053505 (2004-03-01), Chin et al.
patent: 2004/0058508 (2004-03-01), Parat et al.
patent: 2004/0084777 (2004-05-01), Yamanoue et al.
patent: 2004/0089924 (2004-05-01), Yuasa et al.
patent: 2004/0092115 (2004-05-01), Hsieh et al.
patent: 2005/0170661 (2005-08-01), Economikos et al.
patent: 2006/0197228 (2006-09-01), Daubenspeck et al.

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