Semiconductor device manufacturing: process – Chemical etching – Having liquid and vapor etching steps
Reexamination Certificate
1999-10-04
2001-11-20
Hiteshew, Felisa (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Having liquid and vapor etching steps
C438S706000, C438S723000, C438S724000, C438S745000, C438S756000, C438S757000
Reexamination Certificate
active
06319839
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is a method of forming an inter-polysilicon oxide (IPO) layer of superior uniformity between two polysilicon layers (POLY1 and POLY2) in a microelectronics fabrication, such as, but not limited to, the fabrication of a charge coupled device (CCD), so that POLY2 does not undercut the IPO, stringer formation does not occur in POLY2, plasma damage is significantly reduced and fringe electric fields during the operation of the device can be controlled.
2. Description of the Related Art
Certain microelectronics devices, such as charge coupled devices (CCD), are formed by a process in which a silicon substrate is first covered by an oxide-nitride-oxide (ONO) layer (see C. Y. Chang and S. M. Sze, “ULSI Technology,” McGraw-Hill Book Co., N.Y. 1996, p.168). An initial polysilicon (POLY1) layer or a topographic distribution of such layers is then deposited on this ONO substrate. This POLY1 layer is then covered by a polysilicon oxide layer, called the inter-polysilicon oxide layer (IPO), which is formed by wet thermal oxidation. As a final step in the fabrication, a second polysilicon layer (POLY2) is deposited over the IPO layer, Shih et al., U.S. Pat. No. 5,804,488, applies such a process to the formation of capacitors within the fabrication of microelectronic circuitry. Wuu et al, U.S. Pat. No. 5,480,814, discuss the formation of IPO layers over polysilicon gates in the context of the fabrication of certain self-aligned contact (SAC) structures. Liaw et al., in U.S. Pat. No. 5,866,499 discuss the formation of a triple-layer polysilicon structure separated by IPO layers. Yoo, in U.S. Pat. No. 5,470,779, discusses the formation of an SRAM structure in which an IPO is formed by plasma chemical vapor deposition (PE CVD) between a polysilicon layer and a semi-insulating polycrystalline silicon (SIPOS). The process by which the POLY2 layer is deposited over the IPO layer can cause the IPO layer to be undercut, leading to the formation of POLY2 stringers within the undercut area. In addition to the undercutting and stringer formation, the IPO layer may also be subject to non-uniformities as a result of the method of deposition
The present invention provides a method to form IPO layers in such a way as to eliminate the undercutting and stringer formation and increase the uniformity of the IPO.
SUMMARY OF THE INVENTION
A first object of this invention is to provide a method of forming an inter-polysilicon oxide (IPO) layer between two polysilicon layers, POLY1 and POLY2, (the first deposited layer denoted POLY1 and the subsequent deposited layer denoted POLY2) in the fabrication of certain microelectronic devices such as but not limited to a charge coupled device (CCD).
A second object of this invention is to provide a method of forming an IPO layer such that the deposition of POLY2 layer does not undercut the previously deposited IPO layer.
A third object of this invention is to provide a method of forming an IPO layer such that the deposition of POLY2 layer does not produce stringers within the IPO layer as a result of deposition occurring within the undercut area.
A fourth object of this invention is to provide a method of forming an IPO layer such that the deposition of POLY2 layer occurs with a significant reduction of plasma deposition damage.
A fifth object of this invention is to provide a method of forming an IPO layer such that controlled variations of its lateral thickness during formation can be used to control the fringe electric fields produced by the device when in use.
A sixth object of this invention is to provide a method of forming an IPO layer between two polysilicon layers such that said IPO layer is characterized by a higher degree of uniformity than is presently obtainable by other methods.
In accord with the objects of the present invention there is provided a sequence of process steps for depositing a highly uniform IPO layer such that its lateral width can be controlled and such that the deposition of POLY2 layer occurs with no undercutting of the IPO layer, no stringer formation and with a significant reduction of plasma deposition damage.
REFERENCES:
patent: 5470779 (1995-11-01), Yoo
patent: 5480814 (1996-01-01), Wuu et al.
patent: 5796649 (1998-08-01), Keum et al.
patent: 5804488 (1998-09-01), Shih et al.
patent: 5861347 (1999-01-01), Maiti et al.
patent: 5866449 (1999-02-01), Liaw et al.
patent: 5960270 (1999-09-01), Misra et al.
patent: 5977600 (1999-11-01), Wristers et al.
patent: 6162675 (2000-12-01), Hwang et al.
patent: 6180535 (2001-01-01), Wu et al.
patent: 6251719 (2001-06-01), Wang
Chang et al., “ULSI Technology”, The McGraw Hill Companies, Inc., New York, New York, (1996), p. 168.
Chien Wen-Cheng
Wang Jen-Pan
Ackerman Stephen B.
Braun Charlotte A.
Hiteshew Felisa
Saile George O.
Taiwan Semiconductor Manufacturing Company
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