Applique rate converter

Multiplex communications – Wide area network – Packet switching

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Details

370102, H04J 307

Patent

active

045584451

ABSTRACT:
The applique rate converter permits a digital multiplexer to support any data rate less than half of its input port design rate. The applique rate converter develops a composite data stream consisting of alternate data bits and data boundary bits. The data boundary bits change state at each new data bit (corresponding to a change in the data clock.) The composite bit stream is increased to the output data rate by means of a circuit called the `synchronizer`. At the demultiplex side of the applique, the data is separated from the composite stream by a decoding process and, if necessary, the data stream is rate smoothed. The major sections of the applique rate converter are the `synchronizer` at the multiplex side and the data separator and rate smoothing circuits at the demultiplex side.

REFERENCES:
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patent: 3794773 (1974-02-01), Jacob et al.
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patent: 3934093 (1976-01-01), Thyselius
patent: 3987248 (1976-10-01), Platet et al.
patent: 4025720 (1977-05-01), Pachynski
patent: 4079371 (1978-03-01), Shimamura
patent: 4258433 (1981-03-01), Herschtal et al.
patent: 4317198 (1982-02-01), Johnson
patent: 4333176 (1982-06-01), Looschen

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