Boots – shoes – and leggings
Patent
1997-05-19
1999-02-02
Kriess, Kevin A.
Boots, shoes, and leggings
395701, G06F 1500
Patent
active
058674004
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
This invention relates generally to complex application specific integrated circuits and more particularly to a distributed parallel processor architecture and design method which allows such complex integrated circuits to be easily designed.
Integrated circuit technology has advanced in the integration of gates from a small number (fewer that one hundred transistors) to a very large number (millions of transistors). As a result, it is possible to make integrated circuits (ICs) which perform increasingly complex functions and thereby to replace a large number of discrete components, with commensurate benefits in size, cost, and reliability. However, the complexity of the circuits and the large number of available transistors make designing ICs more difficult. Consequently, tools have been developed to help IC designers to design ICs in a more efficient manner. The aim of such tools is to make it easier for the designer to synthesize the target logic without the need to manipulate transistors or gates.
In general purpose processor architecture, primitive low-level instructions (such as add, multiply, compare, etc.) are implemented in hardware which can be sequenced into a programmed set of instructions to implement a complex function. Such an architecture is limited by the throughput achievable by the central processing unit (CPU) which must meet the peak throughput needs for a series of operations. Such a limitation often places a great demand on the hardware and results in inefficiencies in the utilization of designed hardware. In addition, power management of such a centrally controlled architecture is normally difficult.
In order to meet the design throughput goals with an efficient hardware implementation, designers often opt to use application specific integrated circuits design techniques at the cost of sacrificing the system design flexibility offered by post-synthesis programmability.
In general, two approaches have been developed to help IC designers--"standard cell" and "gate array" technologies. These technologies are discussed generally in U.S. Pat. Nos. 5,119,314 (Hotta et al.), 5,173,864 (Watanabe et al.), 5,197,016 (Sugimoto et al.), and 5,283,753 (Schucker et al.). In the standard cell approach, commonly used logic blocks are carefully designed and stored in a cell library. Designers can retrieve and interconnect appropriate logic blocks so as to provide desired functions. Typically, these blocks are primitive logic structures, such as NAND or NOR gates, or other simple logic blocks, such as an adder or multiplier. Logic blocks can be interconnected by routing conductors between the appropriate input/output terminals of the blocks.
Gate array technology involves the fabrication of a large number of base wafers containing identical integrated circuit elements (gates) up to but not including the first level of conductive interconnect. IC designers "customize" the gate array by specifying only the conductive patterns used to interconnect the pre-fabricated gates.
One of the problems with both these approaches is that it is difficult to use them to design ICs which perform complicated functions. This is because the standard cells and gate arrays are primitive or simple logic blocks for all types of applications. Consequently, it takes a lot of time, skill, and effort to integrate these basic building blocks into useful application specific integrated circuits. In addition, the layout and timing constraints and the design effort required to interconnect these logic blocks normally limit the designers freedom and increase the design time.
As an example, circuits used for communication applications typically perform complex signal processing operations. Examples of such circuits are finite impulse response filters, infinite impulse response filters, demodulators, and correlators. These circuits incorporate complicated mathematical algorithms which could be understood and designed only by extremely skilled engineers. Consequently, it is very tedious to implement these c
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patent: 5047949 (1991-09-01), Yamaguchi et al.
patent: 5119314 (1992-06-01), Hotta et al.
patent: 5173864 (1992-12-01), Watanabe et al.
patent: 5197016 (1993-03-01), Sugimoto et al.
patent: 5283753 (1994-02-01), Schucker et al.
"Advanced Computer Architecture" Hwang, pp. 308-309 and 437-445 (1993).
"Introduction to 8080/8085 Assembly Language Programming" Employees of Borland, p. 154 (1990).
El-Ghoroury Hussein
Krause Charles A.
McNeill Dale A.
International Business Machines - Corporation
Kriess Kevin A.
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