Application specific integrated circuit for a serial data bus

Details Application specific integrated circuit for a serial data bus Application specific integrated circuit for a serial data bus

1989-09-15

1992-12-29

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

375 36, 340709, 340711, H04L 700, H04L 2538

Patent

active

051757508

ABSTRACT:
An application specific integrated circuit is disclosed for use with a device locatable on a serial data bus of a data communication system. Attention and synch receiving circuitry is provided for receiving an attention and synch signal being transmitted on the serial data bus for synchronizing the device in accordance with the timing of the attention and synch signals. Demodulation circuitry is provided for receiving a command byte signal and a stop bit signal being transmitted on the serial data bus. Demodulation circuitry is provided for demodulating the command byte signal. Reset circuitry is coupled to the demodulation circuitry for receiving the command byte signal if the command byte signal contains a predetermined reset code. Flush circuitry is coupled to the demodulation circuitry for receiving the command byte signal if that signal contains a predetermined flush code. The flush circuitry clears all device specific data in the integrated circuit in response to the predetermined flush code. Listen circuitry is coupled to the demodulation circuitry for receiving the command byte signal if the command byte signal contains a predetermined listen code. Talk circuitry coupled to the demodulation circuitry is provided for receiving the command byte signal if the command byte signal contains a predetermined talk code. The talk circuitry prepares the integrated circuit to transmit data from the device onto the serial data bus at a later period of time in the data bus transaction.

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