Application specific integrated circuit (ASIC) having improved r

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Patent

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Details

327143, 327198, H03L 706, H03K 302

Patent

active

059125705

ABSTRACT:
Disclosed is a circuit and method for initializing clocked digital logic and for generating at least one clock signal for the clocked digital logic. The circuit includes at least one flip-flop that is responsive to a stimulus signal becoming active for asserting and then deasserting a reset signal to the clocked digital logic. The at least one flip-flop is clocked with a free-running clock signal. The circuit further includes a gating circuit for generating the at least one clock signal from the free running clock signal, and an edge detector that has an input coupled to the at least one flip-flop and an output coupled to the gating circuit. The edge detector operates to cause the gating circuit to place the at least one clock signal into an inactive state at least one period of the free running clock prior to the reset signal being deasserted, and for holding the at least one clock signal in the inactive state for at least one period of the free running clock subsequent to the reset signal being deasserted. In this manner it is guaranteed that no clock edges are applied to the clocked digital logic (e.g., flip-flops) for a predetermined period of time prior to and after the deassertion of the reset signal. The period of the free running clock signal is predetermined to exceed the minimum setup and hold times for the flip-flops that comprise the clocked digital logic.

REFERENCES:
patent: 5323066 (1994-06-01), Feddeler et al.
patent: 5461649 (1995-10-01), Bailey et al.
patent: 5533101 (1996-07-01), Miyagawa
patent: 5535436 (1996-07-01), Yoshida et al.
patent: 5568100 (1996-10-01), Locanthi
patent: 5691659 (1997-11-01), Riley

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