Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
2000-04-12
2001-12-18
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C324S760020, C341S120000, C714S724000
Reexamination Certificate
active
06331770
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor test system for testing semiconductor integrated circuits such as a large scale integrated (LSI) circuit, and more particularly, to a low cost semiconductor test system configured exclusively to a specific application and has an event based tester architecture. The event based semiconductor test system of the present invention is formed by freely combining a plurality of tester modules having identical or different capabilities and a measurement module specific to an intended application where each of the tester module operates independently from one another, thereby establishing a low cost test system. The measurement module may be installed in a test fixture of the test system.
BACKGROUND OF THE INVENTION
FIG. 1
is a schematic block diagram showing an example of a semiconductor test system, also called an IC tester, in the conventional technology for testing a semiconductor integrated circuit (hereafter may also be referred to as “device under test”).
In the example of
FIG. 1
, a test processor
11
is a dedicated processor provided within the semiconductor test system for controlling the operation of the test system through a tester bus. Based on pattern data from the test processor
11
, a pattern generator
12
provides timing data and waveform data to a timing generator
13
and a wave formatter
14
, respectively. A test pattern is produced by the wave formatter
14
with use of the waveform data from the pattern generator
12
and the timing data from the timing generator
13
, and the test pattern is supplied to a device under test (DUT)
19
through a driver
15
.
A response output signal from the DUT
19
is produced in response to the test pattern. The output signal is converted to a logic signal by an analog comparator
16
with reference to a predetermined threshold voltage level. The logic signal is compared with expected value data from the pattern generator
12
by a logic comparator
17
. The result of the logic comparison is stored in a failure memory
18
corresponding to the address of the DUT
19
. The driver
15
, the analog comparator
16
and switches (not shown) for changing pins of the device under test, are provided in a pin electronics
20
.
The circuit configuration noted above is provided to each test pin of the semiconductor test system. Therefore, since a large scale semiconductor test system has a large number of test pins, such as from 256 test pins to 1048 test pins, and the same number of circuit configurations each being shown in Figure are incorporated, an actual semiconductor test system becomes a very large system.
FIG. 2
shows an example of outer appearance of such a semiconductor test system. The semiconductor test system is basically formed with a main frame
22
, a test head
24
, and a work station
26
.
The work station
26
is a computer provided with, for example, a graphic user interface (GUI) to function as an interface between the test system and a user. Operations of the test system, creation of test programs, and execution of the test programs are conducted through the work station
26
. The main frame
22
includes a large number of test pins each having the test processor
11
, pattern generator
12
, timing generator
13
, wave formatter
14
and comparator
17
shown in FIG.
1
.
The test head
24
includes a large number of printed circuit boards each having the pin electronics
20
shown in FIG.
1
. The test head
24
has, for example, a cylindrical shape in which the printed circuit boards forming the pin electronics are radially aligned. On an upper surface of the test head
24
, a device under test
19
is inserted in a test socket at about the center of a performance board
28
.
Between the pin electronics circuit and the performance board
28
, a pin (test) fixture
27
is provided which is a contact mechanism for communication of electrical signals. The pin fixture
27
includes a large number of contractors such as pogo-pins for electrically connecting the pin electronics circuits and the performance board. The device under test
19
receives a test pattern signal from the pin electronics and produces a response output signal.
In the conventional semiconductor test system, for producing a test pattern to be applied to a device under test, the test data which is described by, what is called a cycle based format, has been used. In the cycle based format, each variable in the test pattern is defined relative to each test cycle (tester rate) of the semiconductor test system. More specifically, test cycle (tester rate) descriptions, waveform (kinds of waveform, edge timings) descriptions, and vector descriptions in the test data specify the test pattern in a particular test cycle.
In the design stage of the device under test, under a computer aided design (CAD) environment, the resultant design data is evaluated by using a logic simulation process through a test bench. However, the design evaluation data thus obtained through the test bench is described in an event based format. In the event based format, each change point (event) in the particular test pattern, such as from “
0
” to “1” or from “1”, to “0”, is described with reference to a time passage. The time passage is expressed by, for example, an absolute time length from a predetermined reference point or a relative time length between two adjacent events.
The inventors of this invention has disclosed the comparison between the test pattern formation using the test data in the cycle based format and the test pattern formation using the test data in the event based format in the U.S. patent application Ser. No. 09/340,371. The inventors of this invention have also proposed an event based test system as a semiconductor test system as a new concept test system. The details of the structure and operation of the event based test system is given in the U.S. patent application Ser. No. 09/406,300 owned by the same assignee of this invention.
As described in the foregoing, in the semiconductor test system, a large number of printed circuit boards and the like which is equal to or greater than the number of the test pins are provided, resulting in a very large system as a whole. In the conventional semiconductor test system, the printed circuit boards and the like are identical to one another.
For example, in a high speed and high resolution test system, such as a test rate of 500MHz and timing accuracy of 80 picosecond, the printed circuit boards for all the test pins have the same high capabilities each being able to satisfy the test rate and timing accuracy. Thus, the conventional semiconductor test system inevitably becomes a very high cost system. Further, since the identical circuit structure is used in each test pin, the test system can conduct only limited types of test.
An example of devices to be tested includes a type of semiconductor device which has both an analog function and a digital function. A typical example of which is an audio IC or a communication device IC which includes an analog-digital (AD) converter, a digital-analog (DA) converter and a digital signal processing circuit. Further, there is a type of semiconductor device which has a functionality for testing an inner circuit by itself, i.e., built-in self-test (BIST).
In the conventional semiconductor test system, it is constituted so that only one type of functional test can be conducted at one time. Therefore, to test the mixed signal integrated circuit noted above, each functional block must be tested separately in a series fashion, such as, first testing the AD converter, then testing the DA converter, and after that, testing the digital signal processing circuit. Further, in testing the device having the BIST function, such a test for evaluating the BIST function must be carried out separately from the other types of test.
Even in the case where testing a device which is configured solely by logic circuits, almost always, not all of the pins of such a device under test do not require the highest performance of the se
Advantest Corp.
Metjahic Safet
Muramatsu & Associates
Nguyen Jimmy
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