Electrical computers and digital processing systems: multicomput – Computer network managing
Reexamination Certificate
2003-03-13
2004-03-16
Lim, Krisna (Department: 2153)
Electrical computers and digital processing systems: multicomput
Computer network managing
C709S229000
Reexamination Certificate
active
06708210
ABSTRACT:
COPYRIGHT NOTICE
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the xerographic reproduction by anyone of the patent document or the patent disclosure in exactly the form it appears in the U.S. Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
BACKGROUND OF THE INVENTION
The present invention is generally related to the networking field and more particularly to techniques for providing application user interfaces (APIs) for controlling the functionality of network processors.
The communication industry has experienced explosive growth stemming from increased demand for information and connectivity by both individual consumers and corporations. Due to the proliferation of the personal computer and the rise of communication networks, such as the Internet, there is an ever increasing need for faster communication between computers using efficient networks. In order to accommodate this explosive growth, carriers and backbone providers are rapidly introducing network infrastructures which offer exponentially more bandwidth and information carrying capacity than in the past.
In order to meet the growing demand for speed and bandwidth, network devices such as client computer systems, servers, hubs, routers, switches, network backbones, network processors, etc., are being forced to offer a wide range of services to meet consumer demands. These network processors have to be capable of supporting a plethora of emerging communication standards, transport protocols, and increased performance requirements. These network processors also have to perform a plurality of tasks such as performing translation between different network standards such as Ethernet and Asynchronous Transfer Mode (ATM), reformatting of data, traffic scheduling, routing of data cells, packets, messages, etc.
Although network processors now provide more services, the success or failure of these network processors depends largely on how easily they can be integrated with and controlled by a host device such as a computer. Due to the differing requirements of host applications, it is desired that the network processors provide facilities to perform control functions and network management functions both at a higher level of control and also at a more granular device level. Further, it is desired that the network processors provide facilities allowing host applications to make full use of the resources and services offered by the various existing and emerging networking standards.
SUMMARY OF THE INVENTION
According to the teachings of the present invention, techniques are provided for controlling a network processor and for facilitating integration of the network processor with a host system or an application executing on the host system. The present invention provides application programming interfaces (APIs) which can be invoked by the host system or the host application for performing functions on the network processor. The APIs provided by the present invention allow a host to efficiently use resources and services offered by the network processor.
According to an aspect of the present invention, upper level APIs are provided which allow a host to control the network processor and also perform various network data manipulation functions. The APIs are intended to encapsulate as much as possible the underlying messaging between the host system and the network processor and to hide the low device level command details from the host. In one embodiment, the APIs may be mapped to one or more device level APIs.
According to another aspect of the present invention, the APIs are provided by a upper level program module. A host may invoke an API which is then communicated by the program module to the network processor where functions corresponding to the API are performed. Responses to the APIs may be forwarded synchronously or asynchronously back to the host. In one embodiment of the present invention, asynchronous callback functions, invoked in response to the API calls are used to forward responses to the host.
According to yet another aspect of the present invention, the APIs allow a host to configure and monitor a network processor in the control plane, and to send or receive network data in the data plane. Examples of APIs include APIs for system initialization and configuration, physical layer hardware management functions, ATM signaling, ILMI and related functions, LANE related functions, bridging functions, system facilities functions, system diagnostics, network management functions, and statistics gathering functions. APIs are also provided for performing functions related to upper layer software protocol stacks such as MPOA protocol stack, LANE protocol stack, and IP over ATM protocol stack.
Other aspects and advantages of the invention will be better understood by reference to the following detailed description and the accompanying figures. dr
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1
depicts a simplified block diagram of a network processor according to an embodiment of the present invention;
FIG. 2
depicts a simplified block diagram of the general architecture of a processing engine subsystem according to an embodiment of the present invention;
FIG. 3A
is a schematic diagram illustrating one embodiment of an interface between a host system and the network processor of
FIG. 1
;
FIG. 3B
is a schematic diagram illustrating another embodiment of an interface between a host system and the network processor of
FIG. 1
;
FIG. 3C
is a schematic diagram illustrating a further embodiment of an interface between a host system and the network processor of
FIG. 1
;
FIG. 3D
is a schematic diagram illustrating yet another embodiment of an interface between a host system and the network processor of
FIG. 1
;
FIG. 4A
is a schematic diagram illustrating one embodiment of an upper layer software protocol stack that may utilize one or more APIs;
FIG. 4B
is a schematic diagram illustrating another embodiment of an upper layer software protocol stack that may utilize one or more APIs:
FIG. 4C
is a schematic diagram illustrating a further embodiment of an upper layer software protocol stack that may utilize one or more APIs:
FIG. 5
depicts a simplified block diagram of memory buffers provided by a host system and a network processor for exchanging information according to an embodiment of the present invention; and
FIG. 6
depicts an exemplary memory structure used for encapsulating a command written to the memory buffers according to an embodiment of the present invention.
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Chang Chi-Hua
Trinh Man Dieu
Intel Corporation
Lim Krisna
Tweet Kerry D.
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