Application of thin crystalline Si.sub.3 N.sub.4 liners in shall

Details Application of thin crystalline Si.sub.3 N.sub.4 liners in shall Application of thin crystalline Si.sub.3 N.sub.4 liners in shall

1997-01-21

1998-05-05

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257510, 257649, H01L 2900

Patent

active

057478660

ABSTRACT:
Silicon integrated circuits use a crystalline layer of silicon nitride (Si.sub.3 N.sub.4) in shallow trench isolation (STI) structures as an O.sub.2 -barrier film. The crystalline Si.sub.3 N.sub.4 lowers the density of electron traps as compared with as-deposited, amorphous Si.sub.3 N.sub.4. Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si.sub.3 N.sub.4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si.sub.3 N.sub.4 film is deposited at temperatures of 720.degree. C. to 780.degree. C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050.degree. C. to 1100.degree. for 60 seconds.

REFERENCES:
patent: 4918028 (1990-04-01), Shirai
patent: 5085711 (1992-02-01), Iwamoto et al.

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