Coded data generation or conversion – Analog to or from digital conversion – With particular solid state devices
Reexamination Certificate
2003-05-05
2004-06-15
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
With particular solid state devices
C341S143000
Reexamination Certificate
active
06750794
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a superconducting oscillator/counter analog-to-digital converter (ADC) and, more particularly, to a superconducting oscillator/counter ADC that simultaneously samples in-phase and quadrature-phase RF signals.
2. Discussion of the Related Art
There is a need for high performance and low power ADCs to digitize high frequency analog RF signals for high-speed signal processing applications, such as in radar and communications systems. ADCs of this type are particularly useful in receivers to sample and decipher a received RF signal. There is a push in the industry to move the digital conversion of the received RF signal farther up in the signal processing chain to provide greater processing capabilities. Superconductor ADCs have shown a great potential to achieve superior performance at much lower power than conventional integrated circuit semiconductor-based ADCs. Further, superconducting ADCs can operate at very high sample rates, for example, 10-100 GS/s, allowing conversion of very large bandwidth signals.
Superconductor ADCs employ superconducting logic circuits that use Josephson junctions instead of transistors as used in semiconductor-based circuits. A Josephson junction is a weak link between two superconducting materials where electrons tunnel across the junction. As long as the current through the junction is less than a critical current, the junction will be superconducting. A bias current is applied to the junction that is below the critical current. When additional current, for example, from an analog signal, is applied to the junction so that the current exceeds the critical current, the junction will generate a voltage pulse. The voltage pulse corresponds to a quantum leap in the magnetic phase of the junction, which will create a single flux quantum (SFQ) voltage pulse across the junction. The area of the SFQ voltage pulse generated at the junction is determined by fundamental physical constants and is h/2e, where h is Planks constant (6.6262×10
−34
Joule seconds), and e is the fundamental electrical charge (1.602×10
−19
Coulombs).
The SFQ pulses can be used to transmit data at very high frequencies. The SFQ pulses are transmitted by coupling a series of Josephson junctions together to provide a Josephson transmission line (JTL). When a particular Josephson junction in a JTL receives an SFQ pulse from a preceding Josephson junction, the pulse causes the junction to emit a voltage pulse, so that the SFQ pulse is recreated to continue propagating along the JTL. A discussion of JTLs operating in this manner can be found in U.S. Pat. No. 6,507,234, issued Jan. 14, 2003 to Johnson et al., assigned to the Assignee of this application, and herein incorporated by reference.
Oscillators/counter ADCs that use superconducting Josephson single flux quantum (SFQ) circuits for converting an analog signal to a digital signal are known in the art. U.S. Pat. No. 6,127,960 issued Oct. 3, 2000 to Silver et al. provides a discussion of superconducting oscillator/counter ADCs.
FIG. 1
is a block diagram of a known superconducting oscillator/counter ADC
10
that is capable of simultaneously providing in-phase and quadrature-phase sampling of an RF analog input signal. The ADC
10
can be employed in any suitable superconducting circuit, such as a high frequency receiver that receives an RF analog signal to be digitized for further signal processing to extract the information thereon.
The RF analog signal to be digitized is applied to a superconducting voltage controlled oscillator (VCO)
12
. The VCO
12
can be any superconducting circuit suitable for the purposes described herein. Superconducting VCOs of this type are known in the art, and may employ a single Josephson junction or multiple Josephson junctions for higher resolution. The VCO
12
generates a series of SFQ pulses, where the number of pulses generated for any given period of time is representative of the magnitude of the analog signal at that time.
The SFQ pulses from the VCO
12
are applied to a superconducting pulse splitter
14
that directs the SFQ pulses into an in-phase line
16
and a quadrature-phase line
18
. The pulse splitter
14
is also a known superconducting circuit employing Josephson junctions that generates two SFQ pulses for each SFQ pulse it receives. The in-phase SFQ pulses on the line
16
are applied to an in-phase aperture gate
20
and the quadrature-phase SFQ pulses on the line
18
are applied to a quadrature-phase aperture gate
22
. The aperture gates
20
and
22
are also superconducting logic circuits that employ Josephson junctions, and are well known to those skilled in the art. The aperture gates
20
and
22
are latch type devices that direct the input pulses to a positive or negative output line depending on their internal state. The aperture gates
20
and
22
toggle between their two internal states each time a clock pulse is received. For example, the aperture gates
20
and
22
can be single pole double throw (SPDT) SFQ pulse switches that toggle between two output lines.
The aperture gate
20
receives an in-phase SFQ clock signal from a gate control logic circuit
24
and the aperture gate
22
receives a quadrature-phase SFQ clock signal from the gate control logic circuit
24
. The gate control logic circuit
24
is a superconducting logic circuit that generates the in-phase and quadrature-phase SFQ clock pulses based on SFQ clock pulses from a superconducting master clock
26
. For each SFQ clock pulse from the master clock
26
, the gate control logic circuit
24
alternately provides the in-phase SFQ clock pulses and the quadrature-phase SFQ clock pulses 90° out of phase with each other.
FIG. 2
is a timing diagram showing the analog RF signal applied to the VCO
12
, the SFQ master clock signal, the SFQ input pulses at the output of the VCO
12
, the in-phase SFQ clock signal and the quadrature-phase SFQ clock signal. Each vertical line in the timing diagram represents an SFQ pulse. As is apparent, the spacing between the SFQ input pulses is determined by the magnitude of the analog signal, where the positive peaks of the analog signal provide closely spaced SFQ pulses and the troughs of the analog input signal provide farther spaced SFQ pulses.
The aperture gates
20
and
22
provide the SFQ input pulses on the positive and negative output lines. Each time an SFQ pulse in the in-phase clock signal and the quadrature-phase clock signal is received, the aperture gates
20
and
22
will cause the SFQ input pulses to be switched to the other of the positive output line or the negative output line. In other words, each time an SFQ clock pulse is received, the aperture gates
20
and
22
switch output lines.
The SFQ pulses on the positive and negative output lines from the aperture gate
20
are applied to a superconducting in-phase accumulator
32
and the SFQ pulses on the positive and negative output lines from the aperture gate
22
are applied to a superconducting quadrature-phase accumulator
34
. When the SFQ pulses are provided on the positive line, the accumulator
32
or
34
increments or adds the pulses. When the SFQ pulses are provided on the negative line, the accumulator
32
or
34
decrements or subtracts the pulses. The positive regions (+) between the SFQ pulses in the in-phase clock signal and the quadrature-phase clock signal show the times that the SFQ pulses are being added or incremented, and the negative regions (−) in the in-phase clock signal and the quadrature-phase clock signal show the times that the SFQ pulses are being subtracted or decremented.
The gate control logic circuit
24
provides an in-phase integration clock signal to the accumulator
32
and a quadrature-phase integration clock signal to the accumulator
34
. Each time an SFQ pulse in the in-phase integration clock signal and the quadrature-phase integration clock signal are received by the accumulators
32
and
34
, respectively, the accumulators
Durand Dale J.
Herr Quentin P.
Johnson Mark W.
Jean-Pierre Peguy
Miller John A.
Northrop Grumman Corporation
Warn, Burgess & Hoffmann, P.C.
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