Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means
Reexamination Certificate
2011-08-02
2011-08-02
Nguyen, Thinh T (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular power supply distribution means
C257S204000, C257SE27010, C716S126000
Reexamination Certificate
active
07989849
ABSTRACT:
An integrated circuit has a power rail formed of a first wire in a lower metal layer and a second wire in an upper metal layer and that run in the same direction in their respective layers. A number of vias connect the first and second wires, to form a sandwich power rail structure. Other embodiments are also described and claimed.
REFERENCES:
patent: 5468977 (1995-11-01), Machida
patent: 5723883 (1998-03-01), Gheewalla
patent: 5740102 (1998-04-01), Kawashima
patent: 5742542 (1998-04-01), Lin et al.
patent: 5763907 (1998-06-01), Dallavalle et al.
patent: 5898194 (1999-04-01), Gheewala
patent: 5917228 (1999-06-01), Matsuda et al.
patent: 5923059 (1999-07-01), Gheewala
patent: 5923060 (1999-07-01), Gheewala
patent: 5981987 (1999-11-01), Brunolli et al.
patent: 6091090 (2000-07-01), Gheewala
patent: 6140686 (2000-10-01), Mizuno et al.
patent: 6184726 (2001-02-01), Haeberli et al.
patent: 6194915 (2001-02-01), Nakayama et al.
patent: 6249471 (2001-06-01), Roy
patent: 6306744 (2001-10-01), Aldrich
patent: 6307272 (2001-10-01), Takahashi et al.
patent: 6308307 (2001-10-01), Cano et al.
patent: 6337593 (2002-01-01), Mizuno et al.
patent: 6340825 (2002-01-01), Shibata et al.
patent: 6380798 (2002-04-01), Mizuno et al.
patent: 6445065 (2002-09-01), Gheewala et al.
patent: 6448631 (2002-09-01), Gandhi et al.
patent: 6462978 (2002-10-01), Shibata et al.
patent: 6538945 (2003-03-01), Takemura et al.
patent: 6611943 (2003-08-01), Shibata et al.
patent: 6617621 (2003-09-01), Gheewala et al.
patent: 6683767 (2004-01-01), Ito et al.
patent: 6838713 (2005-01-01), Gheewala et al.
patent: 6842375 (2005-01-01), Raszka
patent: 6912697 (2005-06-01), Shibata et al.
patent: 6938225 (2005-08-01), Kundu
patent: 6941258 (2005-09-01), Van Heijningen et al.
patent: 6998722 (2006-02-01), Madurawe
patent: 7002397 (2006-02-01), Kubo et al.
patent: 7002827 (2006-02-01), Sabharwal et al.
patent: 7069522 (2006-06-01), Sluss et al.
patent: 7073147 (2006-07-01), Ikeda et al.
patent: 7129562 (2006-10-01), Gheewala et al.
patent: 2002/0189910 (2002-12-01), Yano et al.
patent: 2003/0009730 (2003-01-01), Chen et al.
patent: 2003/0102904 (2003-06-01), Mizuno et al.
patent: 2006/0198228 (2006-09-01), Sluss et al.
Knapp, Kevin “Proper Planning Assures SoC Power Integrity—At 90nm and below, avoiding IR drop and electromigration problems becomes a crucial aspect of SoC design”, Dec. 2006/Jan. 2007 Issue of Chip Design Magazine, Internet download http://www.chipdesignmag.com/print.php?articleID=966?issueID=20, Apr. 27, 2007,6 pages.
Non-Final Office Action for U.S. Appl. No. 10/779,194, mailed Apr. 5, 2006, 9 pages.
Non-Final Office Action for U.S. Appl. No. 10/779,194, mailed Sep. 13, 2006, 5 pages.
Non-Final Office Action for U.S. Appl. No. 10/856,520, mailed May 23, 2005, 3 pages.
Non-Final Office Action for U.S. Appl. No. 10/856,520, mailed Aug. 8, 2005, 4 pages.
Non-Final Office Action for U.S. Appl. No. 10/856,520, mailed Oct. 26, 2005, 9 pages.
Non-Final Office Action for U.S. Appl. No. 10/856,520, mailed Jan. 10, 2006, 5 pages.
Non-Final Office Action for U.S. Appl. No. 11/401,806, mailed Jul. 24, 2008, 5 pages.
Non-Final Office Action for U.S. Appl. No. 11/401,806, mailed Oct. 21, 2008, 9 pages.
U.S. Appl. No. 10/779,194, filed Feb. 13, 2004, Inventor Sherlekar et al.
Virage Logic, “Speed Power, ASAP Standard Cell Libraries,” Copyright 2002, Virage Logice Corporation, 4 pages.
Zyuban, V.V. et al., “Low Power Integrated Scan-Retention Mechanism,” (OBM), ISPLED 2002, Aug. 12-14, 2002, pp. 1-8.
Heinecke Darrell
Sherlekar Deepak
Veluri Eswar
Fenwick & West LLP
Nguyen Thinh T
Synopsys Inc.
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