Pulse or digital communications – Synchronizers – Network synchronizing more than two stations
Reexamination Certificate
1998-10-07
2002-04-02
Corrielus, Jean (Department: 2631)
Pulse or digital communications
Synchronizers
Network synchronizing more than two stations
C370S503000
Reexamination Certificate
active
06366630
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an apparatus with a digital interface suitable for dubbing recording by a network conforming to IEEE 1394 standards, and a digital interfacing method
BACKGROUND TECHNOLOGY
Recently, image digital processing has been investigated. Also various systems have been under investigation for digital image data recording by a magnetic recording/reproducing device (VTR). For example, in Japan, the Home Digital VTR (Video Tape Recorder) Council has established SD (Standard Definition) standards for recording a SD signal such as an NTSC signal and a PAL signal as it is, namely, as a digital signal by compressing it, and HD (High Definition) standards for recording an HD signal such as an HDTV (High Definition TV) baseband signal as it is, namely, as a digital signal by compressing it. A home digital VTR (hereinafter, called a DVTR) will be commercially availably soon.
Generally speaking, if an image signal is digitized, its information content becomes enormous. Therefore, it is difficult to transmit or record the digitized signal without compressing it, in view of the communication rate and cost. In the case of the SD standards and the HD standards, a digital image signal is compressed in frames.
FIG. 1
is the recording format of a tape conforming to the SD standards.
FIG. 1
shows a recording track
16
formed on the tape
15
. As shown in
FIG. 1
, the recording track
16
comprises a plurality of areas corresponding to various data kinds. That is, the recording track
16
consists of an ITI (Insert and Track Information) including an SSA (Start-Sync Block Area) and TIA (Track ID Area), an audio area, a video area, a subcode area, etc. These areas are sequentially arranged from the bottom edge to the top edge of the tape
15
. Gaps
1
-
3
as well as an amble part are provided between these areas. When the tape is traced by a magnetic head, the ITI, the audio area, the video area and the subcode area are sequentially recorded or reproduced.
The magnetic head traces the tape according to the timing of a head switch pulse shown in FIG.
2
. The tape is traced by the rotary head at the rise timing and the fall timing of the head switch pulse in FIG.
2
. The head switch pulse is generated synchronously with a frame pulse as shown in FIG.
2
. In the case of the SD standards, as shown in
FIG. 2
, the head traces the tape ten times during one frame period. That is, one frame is recorded on ten tracks.
The time required to trace one track is one tenth of one frame period.
FIG. 3
shows data which is transmitted during one track period. As shown in
FIG. 3
, one track period is 3.33 milliseconds. During this period, all the data recorded in the above-mentioned areas, namely, the ITI, the audio area, the video area and the subcode area are transmitted. The head switch pulse is a reference signal for track recording by the DVTR. Cylinder servo is applied according to this head switch pulse.
In the case of the SD format of a home digital VTR, data is recorded on each track using one sync block as a recording unit. Each sync block is 90 bytes in length and contains 2-byte synchronizing signal (SYNC) and 3-byte ID.
The video area shown in
FIG. 1
contains 2-byte SYNC, 3-byte ID, 77-byte video data area, 8-byte horizontal parity C
1
and 77-byte vertical parity C
2
. The video area contains three video auxiliary data areas (VAUX
0
, VAUX
1
and VAUX
2
), each being one-sync-block long, 135-sync-block long video data area and 11-sync-block long vertical parity C
2
.
The DVTR can record not only an analog TV signal after compressing it but also a digital data directly.
FIG. 4
is a block diagram of the art relating to the DVTR which inputs and outputs digital data only.
IEEE (The Institute of Electrical and Electronics Engineers, Inc.) 1394 which is a low-cost peripheral interface suitable for multimedia applications is now widespread as the unified standards of a digital interface system for data transmission/reception among digital image devices. The IEEE 1394 makes it possible to multiplex a plurality of channels. The IEEE 1394 has an isochronous transfer function which guarantees the transfer of image, audio data, etc., within a given time, so it is the digital interface suitable for image transmission. Published Unexamined Patent Application No. 8-279818 (No. 279818/1996) discloses the IEEE 1394 in detail.
With the device shown in
FIG. 4
, a cable conforming to the IEEE 1394 standards is connected with a terminal
1
. A 1394 circuit
2
is used to control a link layer and a physical layer of a digital interface conforming to the IEEE 1394 standards. The circuit receives data flowing on the 1394 cable (not shown) connected with the terminal
1
and sends the data to a digital I/F packet converter circuit
3
, and at the same time sends data from this packet converter circuit
3
to the 1394 cable.
The digital I/F packet converter circuit
3
converts a packet conforming the IEEE 1394 standards into a packet conforming to the SD standards and vice versa. The 1394 packet is converted into the SD standards packet by the digital I/F packet converter circuit
3
to be fed to a correcting encoding/decoding circuit
5
. In the case of the SD standards, the digital I/F converter circuit
3
converts a one-sync-block long data input into one DIF (Digital Interface) block. At the same time, this converter circuit converts one-track data into a 150 DIF block. The data is input/output in a 150-DIF-block unit.
In addition, the output of the digital I/F packet converter circuit
3
is rearranged by, for example, the correcting encoding/decoding circuit
5
into a data sequence shown in FIG.
1
. The correcting encoding/decoding circuit
5
reads out data stored in a memory
6
, arranges the vertical parity C
2
(outside code) for error correction for the data arranged in the track direction in
FIG. 1
, and arranges the horizontal parity C
1
(inside code) for the data arranged in the sync direction. The error correcting encoding/decoding circuit
5
adds the outside code and the inside code to the data and outputs the data in the format sequence shown in
FIG. 1
to a modulator/demodulator circuit
7
. This error correction processing is controlled by a microcomputer
10
.
The output of the error correcting encoding/decoding circuit
5
is modulated by the modulator/demodulator circuit
7
and is recorded on the tape
9
by an amplifier equalization detecting circuit
8
.
As described above, in the case of the SD standards, one frame is recorded on ten tracks. However, the SD standards do not permit a change to part of the content of the system data in one-frame recording unit. It is impossible to change the data from any track in one frame.
The Home Digital VTR Council is determined to adopt MPEG 2 system as a compression system for the next-generation digital broadcasting, ATV and DVB. The ATV standards and the DVB standards adopt a system which records data compressed by the MPEG 2 system as it is. The SD standards and the HD standards adopt an in-frame compression system. The MPEG 2 system adopts not only in-frame compression but also interframe compression coding. That is, MPEG 2 data has no fixed frame length, and the number of the tracks required for one-frame data recording is variable. Therefore, data is recorded in a track unit, and the subcode, the VAUX and the AAUX are also recorded in a track unit. Accordingly, in this case, the error correcting encoding/decoding circuit
5
can correct an error in a memory which can store data for a few tracks.
That is, in the error correction processing, first, the outside code (C
2
) is encoded, then the inside code (C
1
) is encoded for data containing such is encoded outside code. Therefore, it is necessary for the error correcting encoding/decoding circuit
5
first to store data recorded in the track direction which is required to generate such an outside code in order to add the outside code to the data. Accordingly, to encode the outside code, two memories are required: one memory which can store one
Corrielus Jean
Kabushiki Kaisha Toshiba
Pillsbury & Winthrop LLP
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