Television – Image signal processing circuitry specific to television – A/d converters
Reexamination Certificate
1996-11-29
2001-03-13
Kelley, Chris S. (Department: 2613)
Television
Image signal processing circuitry specific to television
A/d converters
C348S638000, C348S644000
Reexamination Certificate
active
06201578
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus with on A/D converter for processing a color television signal. More specifically, the present invention relates to an apparatus which is utilized in a video recording/reproducing apparatus, a television receiver, and etc., and includes an A/D converter which converts a color television signal into color television signal data (digital color television signal).
2. Description of the Prior Art
In order to sample a color television signal (hereinafter, simple referred to as a television signal); and by an A/D converter in synchronous with a color burst signal included in the television signal, conventionally, a so-called burst PLL (Phase-Locked Loop) is constructed, and a sampling clock is obtained form an output of the PLL.
More specifically, with referring to
FIG. 1
showing prior art, an inputted composite color television signal is applied an A/D converter
3
via a low-pass filter
1
and a pedestal clamp circuit
2
and subjected to an A/D conversion on the basis of a sampling clock which is produced by a PLL and has a frequency of 4 Fsc (four times a frequency of a subcarrier signal).
In the PLL
4
, the composite color television signal is applied to a bandpass filter
4
a
so as to be subjected to a Y/C separation. A chrominance signal component (a burst signal) from the bandpass filter
4
a
is given to a phase comparator
4
b
. The composite color television signal is also applied to a synchronization signal separation circuit
4
c
. A burst gate pulse is produced by a burst gate pulse generation circuit
4
d
on the basis of a horizontal synchronization signal outputted form the synchronization signal separation circuit
4
c
, and the phase comparator
4
b
is enable by the burst gate pulse. Therefore, the phase comparator
4
b
compares a phase of the above-described burst signal with an output of a frequency-division circuit
4
f
which frequency-divides an oscillation signal of a VCO
4
e
having an oscillation frequency of 4 Fsc by 1/N (¼, for example). An output of the phase comparator
4
b
is applied to the VCO
4
e
. Thus, the burst PLL
4
is constructed.
Then, an output of the A/D converter
3
is processed by a 3-dimension Y/C separation circuit
5
a
, etc., in a digital signal processor (DSP)
5
, and applied to D/A converters
6
a
and
6
b
so as to be converted again into an analog luminance signal and an analog chrominance signal. Outputs of the D/A converters
6
a
and
6
b
are further applied to demodulation circuit (not shown) so as to be demodulated with an analog signal processing.
In the prior art of
FIG. 1
, there is a possibility that an indefinite phase error occurs between the sampling clock applied to the A/D converter
3
and the burst signal due to influences of temperature drifts in the bandpass filter
4
a
, the pedestal clamp circuit
2
, etc. Therefore, color demodulation by a digital signal processing cannot be performed properly, and accordingly, as shown in
FIG. 1
, color demodulation is performed after the digital chrominance signal is converted into the analog chrominance signal by the D/A converter
6
B
. Therefore, there are disadvantages in that not only a circuit configuration becomes complex but also a signal processing efficiency is bad.
It is possible to solve the disadvantage in the prior art shown in
FIG. 1
of the indefinite phase error occurring between the sampling clock and the burst signal by
FIG. 2
prior art.
In the prior art circuit of
FIG. 2
, there are provided a phase comparator
7
and a phase shifter
8
in the DSP
5
, and a phase error between the burst signal (burst data) that is converted into a digital signal by the A/D converter
3
and the sampling clock form the VCO
4
e
detected, and a phase of the sampling clock is changed according to the phase error by the phase shifter
8
, and then the sampling clock is applied to the 3-dimension Y/C separation circuit
5
a.
In the prior art of
FIG. 2
, in order to eliminate an influence of noise, it is necessary to average the burst data within one field, for example, and therefore, there is a disadvantage in that it is necessary to provide a memory having a large capacity capable of storing a large number of burst data.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an apparatus capable of obtaining a clock signal which is in synchronous with a digital burst signal with a simple circuit configuration.
In an apparatus according to the present invention, by applying a control signal to a circuit to be controlled, a signal in which at least one of a phase and a level is controlled is outputted from the circuit to be controlled. The apparatus comprises: A/D converter means which performs an A/D conversion of at least an intermittent reference frequency signal included in a television signal; sampling means which samples an output of the A/D converter means in response to a sampling clock and outputs sampled data; comparative signal data generation means which generates comparative signal data that is a constant level during at least a comparison period; comparison means which compares the sampled data and the comparative signal data; and control signal generation means which applies the control signal to the circuit to be controlled on the basis of an output of the comparison means during a period of the reference frequency signal.
The circuit to be controlled is a VCO having an oscillation frequency which is changed by the control signal or a pedestal clamp circuit having a clamp level which is changed by the control signal.
A/D converter means performs the A/D conversion of the at least intermittent reference frequency signal, e.g., a color burst signal of the television signal on the basis of the an oscillation signal (the sampling clock) from the VCO. The output of the A/D converter means is sampled by the sampling means with the reference frequency. The comparative data generation means generates the comparative signal data having a constant level or an approximately constant level during at least the comparison period e.g., luminance signal data or pedestal level data. The control signal is generated on the basis of the output of the comparison means which compares the sampled data and the comparative signal data with each other, and the control signal is applied to the circuit to be controlled, e.g. the VCO or the pedestal clamp circuit during the period of the reference frequency signal (the color burst signal).
In a case where the circuit to be controlled is the VCO, a capacitor of an analog low-pass filter is charged or discharged in response to a high level signal or a low level signal form the comparison means, and therefore, the low-pass filter outputs the control signal by which the oscillation frequency of the VCO is made smaller or larger.
In a case where the circuit to be controlled is the pedestal clamp circuit, a capacitor included in the pedestal clamp circuit is charged or discharged in response to a high level signal or a low level signal from the comparison means, and therefore, the clamp level is made larger or smaller.
In accordance with the present invention, it is possible to generate a clock signal having a fixed phase in relation to the digital reference frequency signal while utilizing a simple circuit configuration. Furthermore, according to the present invention, since the clamp level of the pedestal clamp circuit can be maintained at constant with a simple circuit configuration, it is possible to fully use an entire dynamic range of the A/D converter means.
The above described objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4216493 (1980-08-01), Hosoya
patent: 4291332 (1981-09-01), Kato et al.
patent: 4463371 (1984-07-01), Lewis, Jr.
patent: 4527145 (1985-07-01), Haussmann et
Armstrong, Westerman Hattori, McLeland & Naughton
Kelley Chris S.
Philippe Gims
Sanyo Electric Co,. Ltd.
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