Apparatus utilizing dual compare logic for self checking of func

Details Apparatus utilizing dual compare logic for self checking of func Apparatus utilizing dual compare logic for self checking of func

1992-01-30

1994-01-04

Beausoliel, Jr., Robert W.

Excavating

371 681, 395575, G06F 1116

Patent

active

052766900

ABSTRACT:
An integrated circuit module in which an error detection circuit compares data generated internally on module with data generated externally from another substantially identical module. An error detect output is asserted upon the condition that data generated internally on module and data generated externally from module do not match. A circuit alters the internally generated data by injecting a zero bit and then a one bit data into the internally generated data to thereby generate altered data. Error anticipation control logic generates a test condition, which corresponds to the expected error condition caused by altered data, by first expecting to detect the effect of the injected zero bit and then expecting to detect the effect of the injected one bit. An error-0 comparison circuit compares the actual error detect output with expected error detect output for the zero bit. An error-1 comparison circuit compares the actual error detect output with expected error detect output for the one bit. An error output is asserted if the actual error detect output and the expected error detect output do not match in either of the two cases.

REFERENCES:
patent: 3789144 (1974-01-01), Doyle
patent: 4107649 (1978-08-01), Kurihara
patent: 4792955 (1988-12-01), Johnson
patent: 4903270 (1990-02-01), Johnson
patent: 4924467 (1990-05-01), Criswell

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