Apparatus using a state machine for generating selectable clock

Details Apparatus using a state machine for generating selectable clock Apparatus using a state machine for generating selectable clock

1993-02-01

1996-02-13

Lee, Thomas C.

Boots, shoes, and leggings

395880, 364DIG1, 3642401, 3642403, 3642701, 3642702, G06F 106, G06F 108

Patent

active

054918146

ABSTRACT:
A computer system has a dynamically adjustable speed bus. The dynamic speed bus system decreases the length of the bus cycle accesses required for fast peripherals; but, maintains normal (longer) length bus cycles for slower peripherals. Circuitry is provided to decrease the bus cycle length by increasing the clock frequency to the bus controller which controls the bus. When accessing peripherals that can support only normal length bus cycles, the circuitry of the present invention drives the bus controller with the normal lower clock frequency. When accessing faster peripherals, a higher clock frequency is generated such that the waveform transitions smoothly between the low and high bus frequencies. The dynamic speed bus circuitry of the present invention is divided into two logic sections: 1) a decode section and 2) a clock generation section. The decode section identifies faster peripherals that are compatible with shorter bus cycles.

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