Boots – shoes – and leggings
Patent
1991-03-04
1994-03-08
Robertson, David L.
Boots, shoes, and leggings
364DIG1, 36424341, 364260, G06F 1200
Patent
active
052936058
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
This invention relates to a computer having what is known as a cache.
Conventionally a cache comprises a random access memory or RAM which can be accessed much faster than a main memory store of the computer.
A cache controller monitors calls from the main, or central processing unit (hereinafter called a "CPU") for data and if the cache controller recognises that the requested data is available in the cache RAM memory, the cache memory sends the data direct to the CPU.
In the event that the requested data is not present in the cache, the main memory store is accessed and the data accessed from the main memory store is fed to the CPU and the cache memory to replace data already in the cache memory or to add to it, depending on address location availability.
In a conventional computer, each element of data has an associated address by which the data element is identified. Where a cache is provided, the CPU is capable of receiving from the main memory store and from the cache memory, elements of data arranged as a single word of data and an associated address. Similarly, the cache controller is capable of handling elements of data arranged as a single word of data and an associate address.
Much more powerful CPU's are now available which are capable of processing elements of data comprising a plurality of words of data each having a unique associated address, and memories are known which are capable of storing data elements in this form.
SUMMARY OF THE INVENTION
According to the invention, we provide a computer comprising a CPU, a memory store and a cache comprising a cache memory and a cache controller, the CPU being capable of receiving from a memory store, or from the cache memory, elements of data each arranged as a plurality of words of data associated with a common address, the cache controller inherently only being capable of handling elements of data arranged as a single word of data and an associated address, there being provided a state machine to enable the cache controller to handle elements of data each arranged as a plurality of words of data associated with a common address.
Thus a cache can be used with a more powerful CPU/memory system without having to provide a cache controller which is inherently capable of handling elements of data each arranged as a plurality of words of data associated with a common address.
BRIEF DESCRIPTION OF THE DRAWING
The invention will now be described with reference to FIG. 1 which is a schematic diagram of a computer in accordance with the invention and to FIG. 2 which is a schematic diagram illustrating the association between data and address.
DETAILED DESCRIPTION
Referring to the drawing, there is shown a computer 10 comprising a main or central processing unit (CPU) 11 which in this specific example comprises an Intel i486 microprocessor, a memory store 12, which may be a main memory and/or an auxiliary memory and/or an expansion memory, and a cache 13.
An address bus 14 and a data bus 15 extend between the CPU 11, the main memory store 12, and the cache 13.
The cache 13 comprises a cache controller 16 which in this example comprises an Intel 82385 cache controller and a static random access memory or S.RAM 17.
A state machine 29 is provided which operates in conjunction with the cache controller 16 and the cache memory 17 and memory store 12 as hereinafter explained.
The cache controller 16 monitors the address bus 14 and in the event that the CPU 11 calls for data which is present in the cache memory 17, the cache controller 16 operates as hereinafter explained, to cause the called for data to be fed from the cache memory 17 to the data bus 15 direct to the CPU 11 where it is processed.
This way of retrieving data from the cache memory 17 is very fast compared with retrieving the data from the memory store 12. However, the content of the cache memory 17 is necessarily small.
In the event that the CPU 11 calls for data which is not present in the cache memory 17, the cache controller 16 causes the data to be retrieved dire
REFERENCES:
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patent: 5131083 (1992-07-01), Crawford et al.
patent: 5146582 (1992-09-01), Begun
Wescon 1987, Conference Record, vol. 31, 1987, S. R. Williams et al.: "The NEC .mu.PD71641 Cache Memory Controller", Session 7/2, pp. 1-5.
Electronics & Wireless World, vol 95, No. 1635, Jan. 1989, I. Wilson: "Cacheing in the Chips", pp. 75-77.
Electronik, vol 38, No. 8, 14 Apr. 1989, J. Bodenkamp: "Der 80486: Cache und Coprozessor mit Integriert", pp. 50-60.
Computer Design, vol. 28, No. 21, 1 Nov. 1989, J. Bond: "Cache Controller Chips Erase PC Performance Bottleneck", pp. 32, 34.
Mitsubishi Denki & Kabushiki Kaisha
Robertson David L.
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