Apparatus performing modulo p addition, where operands are expre

Details Apparatus performing modulo p addition, where operands are expre Apparatus performing modulo p addition, where operands are expre

1989-05-01

1991-02-19

Malzahn, David H.

Boots, shoes, and leggings

G06F 772

Patent

active

049949942

ABSTRACT:
In a modulo p arithmetic apparatus operands are represented as powers of a generator so that multiplications can be performed as simple additions. However, this makes actual addition difficult. Additions are therefore performed by means of a modulo (p-1) subtractor circuit (1), a Zech table (2) and a modulo (p-1) adder circuit (3). In order to reduce the size of the Zech table which would otherwise be required, specific values of the output of the subtractor circuit are converted to their negatives modulo (p-1) by means of a converter circuit (15) prior to their application to the Zech table, making use of the fact that each negative modulo (p-1) maps directly to a unique positive number which is often different from the number which was originally converted. For each number which is converted a multiplexer (18), which normally feeds that input operand (y) which is subtracted in the subtractor circuit to one input (12) of the adder circuit, is switched to feed the other input operand (x) to the adder circuit instead.

REFERENCES:
patent: 4742479 (1988-05-01), Kloker et al.
Bliss, "Table Lookup Residue Adder", IBM Tech. Disclosure Bulletin, vol. 11, No. 8, Jan. 1969, pp. 1017-1018.
S. S. Yau et al., "On the Design of Modulo Arithmetic Units Based on Cyclic Groups", IEEE Trans. Computers, vol. C-25, No. 11, 11/76, pp. 1057-1067.
G. A. Jullien, "Implementation of Multiplication Modulo a Prime Number . . . ", IEEE Trans. Computers, vol. C-29, No. 10, 10/80, pp. 899-905.
F. J. MacWilliams, The Theory of Error-Correcting Codes, (North Holland, 1978), pp. 91-92.

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