Electrical transmission or interconnection systems – Switching systems – Plural switches
Reexamination Certificate
2003-03-18
2004-10-12
Sircus, Brian (Department: 2836)
Electrical transmission or interconnection systems
Switching systems
Plural switches
C327S427000
Reexamination Certificate
active
06803680
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to switch devices, and more particularly to solid-state switch devices.
BACKGROUND OF THE INVENTION
Conventional switch devices operate to control the path on which a signal travels. In general, there are two basic types of switch devices in use: electromechanical and solid state. All switches are considered active devices, in that some sort of power supply is required in order to function properly. In electromechanical switches, a contact is provided that physically changes position during the switching process. Solid-state switches do not contain any moving parts and instead use some kind of semiconductor device for the switching process, which are basically either diodes or transistors. In general, diode switches sense current as a control input while switches comprised of transistors sense voltages as control inputs. One example of a transistor-based switch is comprised of a plurality of field effect transistors (FETs). FET switches are generally known to be utilized in connection with high frequency signal transmission, for example, radio frequency (RF).
In general, a FET switch is in an ON state (very low resistance) allowing any signal to pass from the drain to the source of the FET until a control voltage of a predefined amount (pinch-off voltage) is applied to the gate of the FET. When the pinch-off voltage is applied, the FET switches to an OFF state (very high resistance) and prevents any signal passing from the drain to the source of the FET. The advantage of FET switch is that the control voltage applied to the gate of the FET draws very little current, consuming no power in performing the switching function.
A major drawback of FET switches is that in the OFF state, a signal that one may desire to prevent from passing through the FET from the drain to the source applies a voltage at the drain of the FET. This voltage travels through the FET to the gate and adds to the control voltage input. As this voltage becomes greater than the control voltage, the OFF state FET begins to turn ON as shown in the FIG.
1
.
In many of today's product designs, it is often desirable to require a lower control voltage for operation of a switch. For example, it may be beneficial to lower the control voltage of the switch having the exemplary characteristics of
FIG. 1
from 5 volts to 2 volts while maintaining control over the same RF voltage. However, in order to reduce the control voltage of a switch, the RF voltage must be divided across additional FETs connected in series, as is shown in FIG.
2
.
The configuration illustrated in
FIG. 2
reduces the control voltage needed, but increases the resistance in the ON state. To overcome this added resistance, each FET is made larger and thus an increase in die size for the switch is required. This size increase, however, introduces many new problems in the switch, including:
1. The switch costs more, requiring more semiconductor material to manufacture.
2. The switch has poorer isolation, providing less resistance in the OFF state.
3. The switch has greater leakage in the control line, requiring more power to control the switch
Accordingly, there is a need for an improved switch that can control a current output at lower control voltages, while providing the optimum balance of insertion loss, isolation, maximum power handling, harmonic generation suppression, and leakage current in the control signal.
SUMMARY OF THE INVENTION
The present invention is directed to an apparatus, methods and articles of manufacture for a switch having sharpened control voltage. In one embodiment, a switch includes a plurality of field effect transistors (FETs) with a bypass resistance topology coupled across the FETs so as to be in parallel with the FETs. The bypass resistance topology is used to sharpen the control voltage of the switch. According to one embodiment, the bypass resistance topology includes a resistive element coupled across the entire switch (all of the FETs). According to another embodiment, a separate resistive element is coupled across each FET. With either embodiment, the switch may include any number of FETs and have any number of gates. In addition, the switch may use a single-gate FET architecture, a multi-gate FET architecture, or a mixed gate architecture. The apparatus may also utilize a plurality of parallel switches that are each connected to the same source voltage.
According to an exemplary embodiment of the invention, a switch utilizes a plurality of FETs having a total of six gates to allow the switch to operate at a low control voltage without the need to increase device periphery or die size. The switch may include a single-gate FET architecture, a multi-gate FET architecture, or a mixed gate architecture, as long as the total number of gates in the switch equals six.
According to another exemplary embodiment of the invention, a switch includes feed-forward capacitors. The feed-forward capacitors reduce signal distortion and improve the linearity and harmonic noise rejection characteristics of the FETs within the switch and thus lowers the harmonics of the switch. According to one embodiment, the switch includes two feed-forward capacitors. A first feed-forward capacitor connected between the gate and source of an uppermost FET and the second feed-forward capacitor connected between the gate and drain of a lowermost FET
According to still another exemplary embodiment of the invention, a switch includes a gate resistance topology connected between the gates and a control voltage. The gate resistance topology is used to minimize the effects of leakage current and reduce the resistor voltage drop for process points where FET diode leakage is an issue.
These and other features and embodiments of the invention will be more fully understood from the following detailed description that should be read in light of the accompanying drawings.
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Brindle Christopher N.
Kelcourse Mark F.
MIA-Com, Inc.
Rios Roberto J.
Sircus Brian
LandOfFree
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