Apparatus, method, and system for flash memory

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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C365S185240

Reexamination Certificate

active

07619918

ABSTRACT:
Methods, apparatus, systems, and data structures are disclosed, including a plurality of multiple level memory cells, each of the plurality of multiple level memory cells coupled to one of a plurality of wordlines and each of the plurality of multiple level memory cells including a plurality of logical memory pages; a control circuit coupled to the plurality of wordlines, the control circuit operable to progressively program each of the plurality of multiple level memory cells in at least one sequence including separation of the programming of a first logical memory page and a second logical memory page in any one of the plurality of multiple level memory cells by at least N−1 programming operations to memory cells either coupled to a different wordline or included in a different logical even page or a different logical odd page.

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Lee, June, et al., “A 90-nm CMOS 1.8-V 2-Gb NAND Flash Memory for Mass Storage Applications”,IEEE Journal of Solid-State Circuits, vol. 38, No. 11, (Nov. 2003), 1934-1942.

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