Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-04-05
2011-04-05
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S055000, C716S056000, C716S119000, C716S126000, C716S132000
Reexamination Certificate
active
07921391
ABSTRACT:
Apparatus, methods, and computer readable code for computing parameters related to layout schemes of integrated circuits are disclosed herein. In some embodiments, an actual layout scheme is computed, for example, for a netlist. In some embodiments, one o or more layout schemes are scored based on, for example, susceptibility to failure and/or yield in manufacturing.
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Daro Semiconductors Ltd.
Friedman Mark M.
Garbowski Leigh Marie
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