Apparatus, including delay means, for sampling and recovering da

Details Apparatus, including delay means, for sampling and recovering da Apparatus, including delay means, for sampling and recovering da

1976-06-28

1977-07-05

Chapnick, Melvin B.

Boots, shoes, and leggings

307232, 328 63, 328109, G06F 728, H03K 500

Patent

active

040343480

ABSTRACT:
Data and clock bits are sampled by use of two delay means such as shift registers which are enabled at a clock rate which is set so that a first such delay means coupled to receive the bits includes no more than one bit therein at any time. The receipt of a bit substantially at the midway point of the second delay means, which is coupled serially to receive bits from the first delay means, causes a sampling signal to be generated in response to which a determination is made as to whether another bit has been received by the first delay means. Further logic is provided to recover the data bits.

REFERENCES:
patent: 3422425 (1969-01-01), Vallee
patent: 3518555 (1970-06-01), Konotchick, Jr.
patent: 3602828 (1971-08-01), Kurzweil, Jr. et al.
patent: 3646451 (1972-02-01), Shoap
patent: 3663883 (1972-05-01), Olso
patent: 3684967 (1972-08-01), Kelly
patent: 3740655 (1973-06-01), Dickey, Jr.
patent: 3761887 (1973-09-01), Foster et al.
patent: 3792361 (1974-02-01), Sordello et al.
patent: 3927259 (1975-12-01), Brown

Affiliated with

Also associated with

Rating

Apparatus, including delay means, for sampling and recovering da does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus, including delay means, for sampling and recovering da, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus, including delay means, for sampling and recovering da will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-580581