Apparatus having three separated and decentralized processors fo

Details Apparatus having three separated and decentralized processors fo Apparatus having three separated and decentralized processors fo

1992-12-23

1995-11-07

Lim, Krisna

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395800, 39520001, 364DIG1, 3642844, 3642424, 364230, 370 60, 370 601, 370 61, 370 941, G06F 1516, H04J 302

Patent

active

054653312

ABSTRACT:
A parallel, scalable internetworking unit (IU) architecture employing at least two network controllers (NCs), a foreground buffer controller with local memory, a background buffer controller with local memory, a node processor (NP) and a buffer memory. Each network attached to the IU has an individual network controller which communicates with the foreground buffer controller. The foreground buffer controller interfaces with NCs and maintains queueing information. The background buffer controller communicates with the foreground buffer controller for maintaining packets of data as linked lists of buffers in the buffer memory. The NP communicates with both the foreground and background buffer controllers to process stored header information. And, a connection matrix is provided to dynamically interconnect multiple IUs for increased parallel processing of packet traffic and processing.

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