Apparatus for wire routing of VLSI

Details Apparatus for wire routing of VLSI Apparatus for wire routing of VLSI

1992-01-15

1993-09-14

Trans, Vincent N.

Boots, shoes, and leggings

364489, 364488, G06F 1560

Patent

active

052455505

ABSTRACT:
A wiring route is determined between terminals on an integrated circuit on the basis of information concerning the terminals and areas of the integrated circuit through which a wire can be routed. A mesh memory holds information of mesh points of a wiring area partitioned in a mesh-like pattern. A wavefront memory holds information concerning mesh points constituting the leads of searching point arrays. An expansion point extracting unit selects a source point from the mesh points for a succeeding search from the leading mesh points on the basis of costs. Addresses and costs for mesh points neighboring the source point are calculated. A searching point register holds information concerning the mesh points obtained through the calculation. A determination is made of whether or not the mesh points placed in the searching point register can be searched, and if so they are written to the mesh memory. Duplicate information stored in the searching point register is eliminated. It is then determined whether or not the mesh points corresponding to the terminals to be wired are contained in the searching point register. If so, the wiring route is determined and the process concluded.

REFERENCES:
patent: 3617714 (1971-11-01), Kernighan et al.
patent: 3681782 (1972-08-01), Scanlon
patent: 4484292 (1984-06-01), Hong et al.
patent: 4495559 (1985-01-01), Gelatt, Jr. et al.
patent: 4593351 (1986-06-01), Hong et al.
patent: 4752887 (1988-06-01), Kuwahara
S. J. Hong, "Wire-Routing Machines-New Tools for VLSI Physical Design", Proceedings of the IEEE, vol. 71, Jan. 1983, pp. 57-65.
VLSI-Very Large Scale Integration, pp. 257-266.
"A Placement Algorithm for Array Processors" by Chyan et al., IEEE 20th Design Automation Conference, 1983, pp. 182-188.
"A Parallel Processing Approach for Logic Module Placement" by Ueda et al., IEEE Trans. on Computer-Aided Design, vol. CAD-2, No. 1, Jan. 1983, pp. 39-47.

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