Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1998-10-19
2002-10-15
Kizou, Hassan (Department: 2662)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C370S350000, C370S498000, C370S503000, C370S516000, C370S517000, C375S355000, C375S357000, C375S371000, C326S093000, C326S094000
Reexamination Certificate
active
06466589
ABSTRACT:
BACKGROUND OF THE INVENTION
Asynchronous transfer mode, or ATM technology (hereafter “ATM”), may be described broadly as a switched, connection-oriented networking technology. ATM technology embodies a cell-based fast-packet data communication structure which may support data transfer rates from 1.544 Mbps to up to 10 Gbps. Within ATM networks, ATM switches for routing network data support dedicated media connections running in parallel. When data are transferred in an ATM network, a switched virtual circuit (SVC) is established between the sender and the receiver. Supporting the media connections requires that the ATM switches simultaneously support transmission and routing of very large amounts of data. The use of ATM switching technology for intra-network communications is found to eliminate the bandwidth contention and data bottlenecks found on conventional, or non-ATM shared-media networks,. e.g., Ethernet, Token Ring and FDDI. ATM technology, by its dedicated, high-speed data connections or switches, facilitates broadband multiservice networking which will support a virtually unlimited number of users.
As mentioned, ATM data are cell-structured fast-packet structures. The standardized ATM data structure includes a fixed number of serial data bits (i.e., 48 bytes), preceded by a fixed number of bits comprising an information header (i.e., 5 bytes). To capitalize of its ability to distribute large amounts of data very quickly (Gigabit rate), ATM data are switched very quickly, preferably error free at the data bit level, and also aligned in phase at the cell level at process and/or input. Phase misalignment errors in switched cell data result in bit data transfer error. And even small differences in the lengths of leads to various data input interfaces (e.g., at an ATM switch) can result in phase misalignment of data for sampling (switching), and, therefore, bit corruption.
More particularly, the differences in the length of interconnection wires, cables, etc., between the chips (or boards), as well as the phase drift between data and clock signals, can render synchronization of ATM switching data difficult, resulting in bit corruption, especially as operation speeds continue to increase with evolving technology. And various efforts are known which attempt to address the need to maintain the data integrity, at a bit and cell level, without effecting the speed of data throughput. For example, a technical paper by Woeste et al., Digital-Phase Alligner Macro For Clock Tree Compensation With 70 ps Jitter, ISSCC DIGEST OF TECHNICAL PAPERS, pg. 136-137, February, 1996, describes apparatus which attempts to solve conventional problems associated with skew between clock and data signals in high speed data transfer circuitry.
Woeste et al. describes a digital phase aligner (DPA) which is asserted to decrease troublesome chip-to-chip clock skews caused by process and temperature variations of on-chip clock trees in multiple chip synchronization systems having multiple clock domains, such as ATM. The method discussed adjusts the delay of the variable delay to align the output of the clock tree to the clock input of the chip. The delay is added to render the clock tree latency an integral number of cycles. However, because of increased switching speeds of today's ATM technology, implementing delay lines by way of transmission line lengths is not a viable solution. It slows down data throughput. The problem becomes particularly acute when the numbers of switching chips (i.e., referred to by function as transmitters and receivers) increases within a switching system, requiring large numbers of delay lines.
And like Woests, U.S. Pat. No. 4,700,347 to Rettberg et al., DIGITAL PHASE ADJUSTMENT, discloses a digital cell data, phase-adjustment apparatus which utilizes a plurality of delay lines to accommodate clock skew and data phase drift. The outputs of the delay lines are monitored and compared over a specified time, whereby the '347 apparatus selects one of the output signals. The '347 apparatus selects the output signal for use, that is, the signal to be called phase adjusted, by choosing the output signal which is in opposition to that pair of outputs that straddles the most transitions. However, like Woeste, such a scheme presents a complicated way to solve the problem confronting the ATM system designer
In an article by Robert Cordell, A 45-Mbit/s CMOS VLSI Digital Phase Aligner, IEEE JSSC, vol. 23, No. 2, April, 1988, an alternate scheme for phase aligning ATM cell data is described. The Cordell digital phase aligner (DPA) provides an alignment method whereby numerous digital channels may be brought into phase alignment for subsequent synchronous processing, as required in ATM networks. In Cordell's DPA, the DPA hardware takes several samples of all incoming data and uses the multiple samples to adjust the phase of the same incoming digital data. The Cordell DPA utilizes a “metastable-resistant” version of a D-type flip flop for the sampling. Although the metastable state (non-one or non-zero) may be eliminated by use of Cordell's static master-slave D-type flip flop, the input data may still be subject to erroneous sampling by the D-type flip-flop if sampled at its transition. That is, the Cordell D flip flop design is still subject to sampling phase misalign data. Hence, Cordell falls short of its goals.
And a U.S. patent disclosure by Thomas J. Chaney, DIGITAL PHASE ADJUSTMENT CIRCUIT FOR ATM AND ATM-LIKE DATA FORMATS, filed May 6, 1996, describes yet another high speed data transfer circuit which takes advantage of the structure of ATM and ATM-like data formats for increased ATM data-throughput. Chaney utilizes a fixed pattern of data which is sampled multiple times, and implements a phase adjustment decision based on a comparison of the multiple samples. The sample chosen by comparison is then used as “good” data. However, Chaney describes no means which prevent sampling of the “good” data in its meta-stable state. So while Chaney may have the potential for avoiding phase misalignment, it does not provide means which could be used in an ATM switching network to avoid both possible bit and phase adjustment error.
OBJECTS AND SUMMARY OF THE INVENTION
Hence it an object of the present invention to provide novel data verification circuitry for assuring data integrity before ATM cell processing at a bit level, as well as phase aligning the bit data at the cell level to overcome the limitations in conventional ATM switching technology.
It is another object of this invention to provide novel data processing circuitry for aligning a ATM cell formatted data before switching, at both a bit level, and at a synchronized cell level.
It is another object of this invention to provide unique digital circuit element which, when included in data processing circuitry, minimizes and/or eliminates the possibility that bit data to be processed by the circuitry will be sampled at or during a data transitional state.
It is another object of this invention to provide unique circuitry for use in ATM processing/switching system which aligns the phase of out-of-phase ATM data cells arriving at an ATM system circuit element.
In one embodiment, the present invention comprises an anti-meta trap (AMT) circuit for implementation within digital circuitry in order to verify the stability of data to be utilized by the digital circuitry. In particular, the AMT circuit assures that data for processing by the digital circuitry is not sampled in a transitional state and hence being misinterpreted at the bit level, essentially verifying the integrity of each data bit used. To accomplish the verification, the anti-meta trap (AMT) circuit samples each data bit four (4) different times using four distinct bit-related clocking signals realizing two pair (i.e., four) of time-related sampled signals for each data bit. Each pair of sampled signals is compared, which comparison enables the AMT to determine where the anti-meta state of the sampled data bit lies, with respect to the four clocking sign
Kizou Hassan
Logsdan Joe
LandOfFree
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