Apparatus for updating a multi-way set associative cache memory

Details Apparatus for updating a multi-way set associative cache memory Apparatus for updating a multi-way set associative cache memory

1995-02-06

1995-11-28

Gossage, Glenn

Static information storage and retrieval

Magnetic bubbles

Guide structure

395463, 395483, 395487, 36518907, 36518908, G06F 1200, G06F 1212, G11C 700

Patent

active

054716055

ABSTRACT:
A method and apparatus for updating cache memory status bits that depend on match signals of a multi-way set associative cache are disclosed. Faster updating of the status bits is provided by utilizing the fact that there is a match in at most one way of the cache for any read cycle. A first status bit is set to its previous value if no match occurs in any way of the cache. The first status bit is set to a first value if a match has occurred in a first way of the cache and is set to a second value if a match has occurred in a second way of the cache. Fewer transistors are needed to implement the update circuits which, in a preferred embodiment, are realized using complementary metal oxide semiconductor (CMOS) technology. The update circuits may be implemented in an instruction cache translation look aside buffer of a microprocessor for updating least recently used (LRU) array status bits or any cache memory status signals that depend on match signals.

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