Static information storage and retrieval – Plural shift register memory devices
Patent
1990-02-26
1991-08-20
Popek, Joseph A.
Static information storage and retrieval
Plural shift register memory devices
36518902, 36518912, 36523002, 36523003, G11C 804, G11C 700
Patent
active
050420070
ABSTRACT:
A digital storage device is provided that includes a storage unit having a plurality of word storage locations, each of the word storage locations being coupled to a corresponding read enable line and write enable line, and a pointer unit for addressing the read enable lines and the write enable lines to permit data to be written into the word storage locations in a first sequence in a first operating mode and to be retrieved from the word storage locations in a second sequence that is transposed from the first sequence in a second operating mode; and a clock generator coupled to the pointer unit which controls the operation of the pointer unit.
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patent: 4592019 (1986-05-01), Huang et al.
patent: 4751675 (1988-06-01), Knauer
Weste, Neil et al., "Principles of CMOS VLSI Design", Oct. 1985, pp. 204-206.
Mattausch et al., "A Memory-Based High-Speed Digital Delay Line with a Large Adjustable Length", IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 88.
Ruetz et al., "Architectures and Design Techniques for Real-Time Image-Processing IC's", IEEE Journal of Solid-State Circuits, vol. sc-22, No. 2, Apr. 1987.
Zehner et al., "A CMOS VLSI Chip for Filtering of TV Pictures in Two Dimenions", IEEE Journal of Solid-State Circuits, vol. sc-21, No. 5, Oct. 1986.
Eastman Kodak Company
Lane Jack A.
Popek Joseph A.
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