Apparatus for transmitting cells between ATM layer and...

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

Reexamination Certificate

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Details

C370S359000, C370S419000, C370S469000

Reexamination Certificate

active

06487203

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus for transmitting cells between the ATM (Asynchronous Transfer Mode) layer and the physical layer in the ATM protocol, and a method therefor.
2. Description of the Related Art
Generally, the ATM protocol structure is defined by extending the conventional N-ISDN (Narrowband Integrated Services Digital Network) protocol structure according to the OSI (Open Systems Interconnection) layer model. Each layer provides inherent functional services with the help of the next lower layer's services. The ATM protocol structure fundamentally consists of physical layer, ATM layer, ATM adaptation layer (AAL), and higher layer. See U.S. Pat. No. 5,852,606 to Jeff Prince et al. entitled Method And Apparatus For Transmitting Cells Across An ATM Switch Bus, incorporated herein by reference.
The physical layer further includes physical medium sublayer (PM) and transmission convergence sublayer (TC), providing the transmission resources for carrying ATM cells. The ATM layer provides the ATM communication regardless of transmission system, performing multiple partitioning of cells, selection of a virtual channel and path and generation and deletion of cell headers. The AAL divides information into uniform lengths adapted to construct cells between the ATM layer and higher layer. In this case, it also serves to absorb the accompanying quantization effect, compensate for cell losses and errors due to transmission error or excess, and shield the inherent operation of the ATM layer from the higher layer.
The cell format between the low speed ATM board assembly (LSAA) and low speed physical layer board assembly (LSPA) of the presently developed ATM ESS switch matching has a dummy header of 3 bytes. Namely, the cell transmission system between the ATM layer and physical layer in the conventional low speed subscriber's board employs a proprietary cell format as shown in FIG.
1
. This conventional cell format consists of a proprietary dummy header of 3 bytes, a header field of 5 bytes, and an information field of 48 bytes. The header field and information field as defined in the standard cell includes generic flow control (GFC) region, virtual path identifier (VPI) region, virtual channel identifier (VCI) region, payload type (PT) region, header error control (HEC) region, and cell loss priority (CLP) region. Namely, the above cell format has the proprietary field of 3 bytes compared to the cell format proposed by the ATM forum.
In addition, the procedure for transmitting a cell from LSAA to LSPA is the kind of broadcast employing the multiplexer, which requires each board to check the board bit map of 16 bits to determine whether the received cell belongs to itself, and to transmit the cell through the corresponding port determined by checking the link number if it belongs to the board. On the contrary, the procedure for transmitting a cell from LSPA to LSAA is the kind of direct status that the cell is transmitted in response to an enable signal after the Clav (Cell Available) signal is transmitted to the ATM layer with a header of 3 bytes attached to the cell of 53 bytes. Hence, such system suffers the following drawbacks:
First, the proprietary cell format not defined by the ATM forum makes it impossible to use commercially available parts, and difficult to export the technological product. In addition, there must be used the complex cell format with a large overhead. Second, the cell transmission is carried out by a hybrid procedure which consists of the broadcast method employing the multiplexer (MUX) from LSAA to LSPA and the direct status indication method from LSPA to LSAA.
Besides, the multiplexing polling of the UTOPIA (Universal Test and Operation Physical Interface for ATM) level 2 is based on 31 ports, which are divided into eight (8) groups respectively polled. This is not suitable for the matching module supporting 64 ports.
An example of another method and apparatus for processing cells in an ATM communication system is provided by U.S. Pat. No. 5,748,631 to Paul V. Bergantino et al. entitled Asynchronous Transfer Mode Cell Processing System With Multiple Cell Source Multiplexing.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an apparatus and a method for transmitting cells between the ATM layer and physical layer by employing the standard cell format.
It is another object of the present invention to provide an apparatus and a method for transmitting cells between the ATM layer and physical layer, where the physical layer is divided into uniform groups multiplexly polled by the ATM layer.
It is still another object of the present invention to provide an apparatus and a method for transmitting cells between the ATM protocol layers according to the ATM standard.
According to the present invention, a method of transmitting a cell between the ATM layer and the physical layer is provided for the ATM matching system, which includes the physical layer divided into a specified number of uniform physical device groups multiplexly polled by the ATM layer. The method comprises the steps of multiplexly polling the physical device groups by the ATM layer, transmitting an enable signal to the polled device upon receipt of a state signal from the physical layer, transmitting the cell to the physical layer, checking the multiplexed polling of the ATM layer by the physical layer, writing a physical port number into the cell with transmitting a state signal to the ATM layer upon receipt of the multiplexed polling, and transmitting the cell to the ATM layer upon receipt of an enable signal from the ATM layer.
The present invention will now be described more specifically with reference to the drawings attached only by of example.


REFERENCES:
patent: 5485456 (1996-01-01), Shtayer et al.
patent: 5748631 (1998-05-01), Bergantino et al.
patent: 5784370 (1998-07-01), Rich
patent: 5852606 (1998-12-01), Prince et al.
patent: 5889778 (1999-03-01), Huscroft et al.
patent: 5978377 (1999-11-01), Kim et al.
patent: 6075786 (2000-06-01), Kunito
patent: 6243382 (2001-06-01), O'Neill et al.
patent: 6266324 (2001-07-01), Kirino et al.
patent: 6266748 (2001-07-01), Bishop
patent: 6269096 (2001-07-01), Hann et al.
patent: 6307858 (2001-10-01), Mizukoshi et al.

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