Apparatus for transmitting and receiving data

Details Apparatus for transmitting and receiving data Apparatus for transmitting and receiving data

2004-05-20

2008-11-04

Payne, David C. (Department: 2611)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C375S290000, C375S291000

Reexamination Certificate

active

07447278

ABSTRACT:
The apparatus for transmitting and receiving data according to the invention contains a transmitter (1) for serial data transmission and a receiver (3) for receiving a transmitted data signal (g(t)). The receiver (3) in turn comprises a first sample latch (11) for sampling the received data signal (g(t)) with a first clock (f2) and for generating a first sample value (an). The receiver (3) also comprises a second sample latch (13) for sampling a first shifted received data signal (g(t)+V1) with a second clock (f1) and for generating a second sample value (yn). The receiver (3) further comprises a third sample latch (14) for sampling a second shifted received data signal (g(t)−V1) with the second clock (f1) and for generating a third sample value (zn). Finally the receiver (3) comprises a logic unit (15) for recovering data (dn) out of said first, second and third sample values (an, yn, zn).

REFERENCES:
patent: 6731683 (2004-05-01), Fiedler et al.
patent: 2005/0111585 (2005-05-01), Stojanovic et al.
Dally, William J. “Transmitter Equalization for 4-GBPS Signaling,” IEEE Micro, Jan./Feb. 1997, pp. 48-56.
Kim, J. and Mark A. Horowitz. “Adaptive Supply Serial Links With Sub-1-V Operation and Per-Pin Clock Recovery,” IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1403-1413.

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