Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-03-01
2001-11-27
Kim, Jung Ho (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000
Reexamination Certificate
active
06323722
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to electronic circuitry and, more particularly, to a charge pump for producing a negative substrate bias in a complementary metal oxide semiconductor (CMOS) integrated circuit.
MOS transistors are commonly used in electronic circuits such as dynamic random access memories (DRAMS). In an NMOS transistor, an N-type source region is separated from an N-type drain region by a P-type channel region. All three regions are formed in a P-type semiconductor substrate. By applying a positive voltage to a gate electrode disposed above the channel region, electrons gather in the channel region between the source region and the drain region to allow current to flow from the drain region to the source region. PMOS transistors have the same structure except the conductivity types of the various regions are reversed and a negative gate voltage is required to allow current to flow from the source region to the drain region.
It has been found that NMOS transistors operate better when the P-type substrate of the NMOS (or of the NMOS transistors in a CMOS circuit) is driven negative with respect to circuit ground, in other words there is a negative substrate bias. Such a negative substrate bias provides a number of advantages in terms of the overall circuit performance. More specifically, a negative substrate bias decreases the NMOS transistor source and drain capacitance, decreases the likelihood of latchup, decreases PN diode injection when a node is driven below ground, and decreases the effective body effect, all of which are desirable in CMOS circuits.
Typically a charge pump circuit is used to create the negative substrate bias. Once a negative substrate bias is achieved, however, it does not last forever. For example, when an NMOS transistor is conductive with a relatively high drain to source voltage, some of the electrons traveling from the source region to the drain region collide with atoms in the channel region with enough energy to cause electron/hole pairs to form. The positive gate voltage attracts the generated electrons to the surface of the channel while the positive drain voltage attracts them to the drain where they simply add to the normal flow of electrons from source to drain. The positively charged holes, by contrast, are repelled by the positively charged gate away from the channel region into the substrate. The substrate current created by the excess holes makes the substrate more positively charged, thus counteracting the negative substrate bias. In DRAMS, a substantial amount of substrate current is generated whenever the memory is read or written, since many transistors are switched on and off at that time. This component of substrate current may be orders of magnitude above the background (i.e., standby) leakage current of all the reverse biased P-N diodes throughout the circuit. Therefore, the charge pump must remove low substrate current during standby and high substrate current during high activity to maintain the negative substrate bias.
FIG. 1
is a conceptual schematic diagram of a charge pump
2
which includes a first switch
4
coupled between a positive power supply voltage (V
cc
) and a first terminal
6
of a capacitance C
1
. A second switch
8
is coupled between a ground potential (V
ss
) and a second terminal
10
of capacitance C
1
. A third switch
12
is coupled between (V
ss
) and terminal
6
of capacitance C
1
, and a fourth switch
14
is coupled between the substrate (represented by the voltage (V
bb
)) and terminal
10
of capacitance C
1
. In operation, switches
4
and
8
are both closed (made conductive) for charging capacitance C
1
to a voltage equal to the difference between (V
cc
) and (V
ss
). In
FIG. 1
, (V
cc
)=+5 volts and (V
ss
)=0 volts, so capacitance C
1
charges with node
6
five volts more positive than node
10
. Thereafter, switches
4
and
8
are opened and switches
12
and
14
are both closed. Since the positive terminal
6
of capacitance C
1
is now coupled to a ground potential, the negative terminal
10
of capacitance C
1
tries to drive V
bb
to negative 5 volts through switch
14
. Thereafter, switches
12
and
14
are opened, and the sequence repeats itself. An oscillator (not shown) typically controls the repetitive switching sequence, and a detector (not shown) monitors the substrate voltage and controls the pumping operation to maintain the substrate at the proper negative voltage level.
As discussed in more detail below, known charge pumps consume a substantial amount of power (often 1 milliwatt or more even when no further pumping is required), often work against themselves by adding positive substrate current as they operate, and generally operate inefficiently.
SUMMARY OF THE INVENTION
The present invention is directed to a charge pump which consumes only a very small amount of power (approximately 50 microwatts or less in the exemplary embodiment described herein when no additional pumping is required). The charge pump according to the present invention does not add substrate current as it operates, and operates more efficiently than known charge pumps. In one embodiment of the present invention, a low voltage regulator on the integrated circuit generates a low voltage supply on the integrated circuit for powering a variable frequency oscillator, whose nodes oscillate between ground and the regulated low voltage supply of, for example, about 1.5 volts. The low voltage regulator provides a slightly higher voltage until some negative substrate bias is achieved, assuring proper start-up operation of the oscillator. The low voltage supply dramatically reduces power consumption of the oscillator compared to known oscillators. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed (i.e., when the substrate voltage is at or below the desired negative bias voltage level and the circuit is in standby), and operates at a much higher frequency when charge pumping is needed or likely will be needed. For example, the charge pump will be needed when the substrate voltage is more positive than the desired negative bias voltage level, and may be needed when the integrated circuit is operating in a mode which typically generates high substrate currents. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump.
Voltage translation circuitry translates the negative substrate voltage into a positive voltage signal (e.g., between 0 and +5 volts). This allows the (translated) substrate voltage to be compared to a positive reference voltage using a conventional comparator, without adding substrate current as it operates. When the substrate voltage is more positive than the desired level, the comparator generates a pump activating signal to a pump signal generator which turns on the charge pump.
In one embodiment, the charge pump itself uses an NMOS transistor to perform the switching function of switch
14
of
FIG. 1
in a configuration that neither loses a threshold voltage when conducting nor allows P-N diode injection into the substrate when node
6
of capacitor C
1
is driven low by switch
12
. Likewise, all other switches
4
,
8
, and
14
do not exhibit a threshold voltage drop. In an exemplary embodiment, the one-stage pump of the present invention is capable of pumping the substrate to a voltage of −4.9 volts when operating from a supply of +5.0 volts (with the regulator disabled).
A better understanding of the nature and advantages of the charge pump circuit of the present invention may be had with reference to the detailed description and the drawings below.
REFERENCES:
patent: 4336466 (1982-06-01), Sud et al.
patent: 4455493 (1984-06-01), Morton et al.
patent: 4705966 (1987-11-01), Van Zanten
patent: 4710647 (1987-12-01), Young
patent: 4733108 (1988-03-01), Truong
patent: 4754168 (1988-06-01), Liran
patent: 4883976 (1989-11-01), Deane
patent: 4920280 (1990-04-01), Cho et
Kim Jung Ho
Townsend and Townsend / and Crew LLP
Townsend and Townsend and Crew LLP
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