Boots – shoes – and leggings
Patent
1991-08-05
1994-01-04
Lee, Thomas C.
Boots, shoes, and leggings
395425, 364DIG1, 3642464, 364252, 3642544, 3642551, G06F 1206
Patent
active
052768260
ABSTRACT:
A computer system having a multi-module memory system. Accesses to the memory modules for reading or writing are undertaken in parallel. The memory system is addressed by input addresses. The memory system includes a map unit for transforming the input addresses to output addresses in a pseudo-random manner so as to tend to distribute memory accesses uniformly among the memory modules whereby contention resulting from multiple concurrent attempts to access the same memory module is reduced. The map unit performs addresses transforms that are repeatable so that the same input address maps to the same output address and that are one-to-one such that each input address maps to one and only one output address.
REFERENCES:
patent: 3675215 (1972-07-01), Arnold et al.
patent: 4051551 (1977-09-01), Lawrie et al.
patent: 4189767 (1980-02-01), Ahuja
patent: 4215402 (1980-07-01), Mitchell et al.
patent: 4254463 (1981-03-01), Busby et al.
patent: 4318175 (1982-03-01), Hawley
patent: 4322815 (1982-03-01), Broughton
patent: 4356549 (1982-10-01), Chueh
patent: 4380797 (1983-04-01), Desyllas et al.
patent: 4400768 (1983-08-01), Tomlinson
patent: 4433389 (1984-02-01), York et al.
patent: 4464713 (1984-08-01), Benhase et al.
patent: 4484262 (1984-11-01), Sullivan et al.
patent: 4511964 (1985-04-01), Georg et al.
patent: 4539637 (1985-09-01), DeBruler
patent: 4550367 (1985-10-01), Hattori et al.
patent: 4707781 (1987-11-01), Sullivan et al.
patent: 4736287 (1988-04-01), Druke et al.
patent: 4754394 (1988-06-01), Brantley, Jr. et al.
patent: 4833599 (1989-05-01), Colwell et al.
patent: 4920477 (1990-04-01), Colwell et al.
patent: 4980822 (1990-12-01), Brantley, Jr. et al.
patent: 5036454 (1991-07-01), Rau et al.
patent: 5083267 (1992-01-01), Rau et al.
patent: 5111389 (1992-05-01), McAuliffe et al.
patent: 5121502 (1992-06-01), Rau et al.
patent: 5133061 (1992-07-01), Melton et al.
Carter et al., "Class of Fast Hash Functions Using Exclusive Or,"IBM Tech Disc. Bull., vol. 19, No. 12, May, 1977, pp. 4822-4823.
J. M. Frailong, W. Jalby and J. Lenfant, "XOR-Schemes: A Flexible Data Organization in Parallel Memories", Proc. of the 1985 Int'l. Con. on Parallel Processing, pp. 276-283, Aug. 1985.
B. R. Rau, C. D. Glaeser and R. L. Picard, "Efficient Code Generation for Horizontal Architectures: Compiler Techniques and Architectural Support"; IEEE, 1982, pp. 131-139.
B. R. Rau and C. D. Glaeser, "Some Scheduling Techniques and an Easily Schedulable Horizontal Architecture for High Performance Scientific Computing", IEEE, 1981, pp. 183-198.
A. Norton and E. Melton, "A Class of Boolean Linear Transformations for Conflict-Free Power-of-Two Stride Access", Proceedings of the 1987 International Conference on Parallel Processing, pp. 247-254, 1987.
Rau Bantwal R.
Schlansker Michael S.
Fagan Matthew C.
Hewlett--Packard Company
Lee Thomas C.
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