Apparatus for transferring information between an interrupt prod

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395500, 3642323, 364DIG1, G06F 1134

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active

054974569

ABSTRACT:
A micro processor emulator in which a set of core micro processor registers are the communication interface between an external system and a core-ported memory. The registers are connected to a serial scan port for transfer of information between a halted emulation environment and the external system. The serial port includes a command register that receives a jump address to initiate execution of a software monitor. Two special bits are provided in the command register, one that indicates a break, and one that indicates a Fast Break GO. This provides a break mechanism for a micro processor chip which does not have a dedicated memory bus. This break mechanism is the mechanism by which a halt or an asynchronous break is effected. After a fast break, the Fast Break GO mechanism does the action described by one command, and then immediately goes back to emulation without any external processor intervention.

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